Worked example

Worked Example for Test-Mode SDC focuses on test SDC completeness, false test-path violations, test constraint audit score. The goal is to convert metric movement into mechanism, owner, and release decision.

A release review shows regression on test SDC completeness, false test-path violations, test constraint audit score. The strongest first move is to freeze evidence, isolate one failing bucket, and prove mechanism before changing flow knobs.

Sequence under inspection

DFT FLOW - Test-Mode SDC

scan insertion -> chain stitch -> compression map -> ATPG -> tester apply -> diagnosis
      |                |                |            |             |
 controllability   shift balance    channel use   coverage     silicon correlation

Primary metric: test SDC completeness, false test-path violations, test constraint audit score

Test SDC contract

test clocks + test enables + mode exceptions
    -> shift/capture timing checks
    -> legal test closure

1. Capture failing report and exact run tags.

2. Tag scenario (mode, lot/corner, pattern class).

3. Trace first dependency that changed.

4. Compare against test-mode SDC, constraint audit report, test path summary.

5. Choose one reversible fix and predefine regression checks.

Did the fix work?

BEFORE / AFTER - Test-Mode SDC

metric quality
  ^
  |                    --- release target
  |      o regressed
  |           o baseline
  |                o after fix
  +-------------------------------> closure iteration

Prove quality, timing, and test-power all moved safely.

DFT deep dive

Test signoff fails when shift/capture timing and test power are treated independently.

Concept diagram

TEST SIGNOFF LOOP

test SDC -> shift/capture timing -> power-aware ATPG -> IR validation -> release

Metric graph

TEST CURRENT

functional current  baseline
scan shift current  peak-risk zone

Reports and artifacts

• test-mode STA report

• shift/capture split

• test power IR map

• waiver tracker

Mini case study

At-speed patterns passed timing but failed in production due to peak shift IR; staggered capture and power-aware fill resolved.

Debug branches

• Tag test and functional corners separately

• Check hold in shift mode

• Correlate fail bins with power hotspots

Senior review question

Ask: what evidence proves this DFT decision is safe for production?

Key takeaways

• State metric, lot/corner context, and pattern tag with every claim.

• Treat timing, power, and quality as one signoff problem.

Common pitfalls

• Chasing coverage without legality checks.

• Ignoring test-power side effects of pattern changes.

• Debugging silicon without reproducible tags.

Principal DFT review addendum

Dedicated test SDC captures scan clocks, test enables, and exceptions needed to analyze shift and capture behavior correctly.

Metric: test SDC completeness, false test-path violations, test constraint audit score