Scan-Ready RTL: Worked Example

Worked example

Worked Example for Scan-Ready RTL focuses on DFT lint pass rate, uncontrollable register count, black-box scan escapes. The goal is to convert metric movement into mechanism, owner, and release decision.

A release review shows regression on DFT lint pass rate, uncontrollable register count, black-box scan escapes. The strongest first move is to freeze evidence, isolate one failing bucket, and prove mechanism before changing flow knobs.

Sequence under inspection

DFT FLOW - Scan-Ready RTL

scan insertion -> chain stitch -> compression map -> ATPG -> tester apply -> diagnosis
      |                |                |            |             |
 controllability   shift balance    channel use   coverage     silicon correlation

Primary metric: DFT lint pass rate, uncontrollable register count, black-box scan escapes

Scan insertion flow

scan-ready RTL -> scan insertion -> stitch -> DRC -> ATPG handoff

1. Capture failing report and exact run tags.

2. Tag scenario (mode, lot/corner, pattern class).

3. Trace first dependency that changed.

4. Compare against DFT lint report, non-scan element list, waiver manifest.

5. Choose one reversible fix and predefine regression checks.

Did the fix work?

BEFORE / AFTER - Scan-Ready RTL

metric quality
  ^
  |                    --- release target
  |      o regressed
  |           o baseline
  |                o after fix
  +-------------------------------> closure iteration

Prove quality, timing, and test-power all moved safely.

DFT deep dive

Scan architecture quality determines whether ATPG can control and observe real silicon state.

Concept diagram

SCAN INSERTION FLOW

scan-ready RTL -> scan replacement -> stitch chains -> DRC -> ATPG handoff

Metric graph

CHAIN BALANCE

chain length spread
low spread   = better shift time
high spread  = routing + hold risk

Reports and artifacts

• scan insertion summary

• chain balance report

• scan DRC log

• clocking legality report

Mini case study

Coverage plateau traced to non-scan flops in reset islands; RTL + DFT lint policy fixed root cause.

Debug branches

• Check scan replacement first

• Audit chain legality by domain

• Validate shift/capture clocks

Senior review question

Ask: what evidence proves this DFT decision is safe for production?

Key takeaways

• State metric, lot/corner context, and pattern tag with every claim.

• Treat timing, power, and quality as one signoff problem.

Common pitfalls

• Chasing coverage without legality checks.

• Ignoring test-power side effects of pattern changes.

• Debugging silicon without reproducible tags.

Principal DFT review addendum

RTL coding style controls scanability through reset style, clock gating discipline, and avoiding structures that block controllability/observability.

Metric: DFT lint pass rate, uncontrollable register count, black-box scan escapes