Debug playbook

Debug Playbook for Scan-Ready RTL focuses on DFT lint pass rate, uncontrollable register count, black-box scan escapes. The goal is to convert metric movement into mechanism, owner, and release decision.

Debug aims to find the first incorrect assumption, not the loudest downstream symptom. Start with reproducibility and ownership.

Root-cause tree

ROOT-CAUSE TREE - Scan-Ready RTL

DFT lint pass rate, uncontrollable register count, black-box scan escapes regresses
        |
  setup changed?
    /        \
  yes         no
  |            |
constraint    silicon or
or ATPG       physical/test path
 /    \          |
SDC   model    chain/clock/power/diagnosis
diff  diff     isolate first failing signature

1. Freeze run tags for patterns, constraints, and tester setup.

2. Isolate first failing metric bucket and scenario.

3. Classify failure source: model, constraints, physical, or silicon.

4. Prove mechanism with one reduced replay or targeted run.

5. Apply smallest owner-controlled fix.

6. Re-run timing, power, and quality regression matrix.

Review memo template

STAFF DFT REVIEW MEMO - Scan Fundamentals / Scan-Ready RTL

1. Symptom
   - Watched metric: DFT lint pass rate, uncontrollable register count, black-box scan escapes
   - Failing scenario: <mode/lot/corner/program>
   - Pattern class: <scan/transition/compressed/BIST/JTAG>
   - Tags: <constraints, patterns, tester program, netlist>

2. Mechanism hypothesis
   - Primary mechanism: RTL coding style controls scanability through reset style, clock gating discipline, and avoiding structures that block controllability/observability.
   - Competing hypothesis: <constraint issue, model issue, physical issue, silicon issue>
   - Missing evidence: <report, replay, diagnosis trace>

3. Proposed action
   - Minimal reversible change: <constraint fix, architecture tweak, pattern update>
   - Expected metric movement: <delta>
   - Regression risk: timing, power, quality, schedule

4. Signoff
   - Re-run artifact: DFT lint report, non-scan element list, waiver manifest
   - Required owners: RTL owner, DFT owner, verification owner
   - Final decision: release, waive, rollback, or escalate

DFT deep dive

Scan architecture quality determines whether ATPG can control and observe real silicon state.

Concept diagram

SCAN INSERTION FLOW

scan-ready RTL -> scan replacement -> stitch chains -> DRC -> ATPG handoff

Metric graph

CHAIN BALANCE

chain length spread
low spread   = better shift time
high spread  = routing + hold risk

Reports and artifacts

• scan insertion summary

• chain balance report

• scan DRC log

• clocking legality report

Mini case study

Coverage plateau traced to non-scan flops in reset islands; RTL + DFT lint policy fixed root cause.

Debug branches

• Check scan replacement first

• Audit chain legality by domain

• Validate shift/capture clocks

Senior review question

Ask: what evidence proves this DFT decision is safe for production?

Key takeaways

• State metric, lot/corner context, and pattern tag with every claim.

• Treat timing, power, and quality as one signoff problem.

Common pitfalls

• Chasing coverage without legality checks.

• Ignoring test-power side effects of pattern changes.

• Debugging silicon without reproducible tags.

Principal DFT review addendum

RTL coding style controls scanability through reset style, clock gating discipline, and avoiding structures that block controllability/observability.

Metric: DFT lint pass rate, uncontrollable register count, black-box scan escapes