Reports & Metrics for Scan-Ready RTL focuses on DFT lint pass rate, uncontrollable register count, black-box scan escapes. The goal is to convert metric movement into mechanism, owner, and release decision.
A report should support a release decision for DFT lint pass rate, uncontrollable register count, black-box scan escapes. One headline number is rarely enough without setup tags and bucket-level evidence.
METRIC GRAPH - DFT lint pass rate, uncontrollable register count, black-box scan escapes
quality metric
^
| target
| - - - - - - -
| o after fix + regression
| o
| o baseline
| o regressed run
+--------------------------------------> closure iteration
input audit focused fix signoff review
Readout:
- explain what moved, why it moved, and who approved itPATTERN HISTOGRAM - Scan-Ready RTL
pattern count
| ***
| *******
| ***********
|************* <- high-volume tail (optimize here)
+--------------------> pattern buckets
smoke stuck-at transition diagnosis
Balance quality and tester limits together.Track DFT lint pass rate, uncontrollable register count, black-box scan escapes by context and pattern class.
Review trend and bucket detail together.
Keep quality, timing, and power metrics in one dashboard.
Store each metric next to the artifact and run tag.
Scan architecture quality determines whether ATPG can control and observe real silicon state.
SCAN INSERTION FLOW
scan-ready RTL -> scan replacement -> stitch chains -> DRC -> ATPG handoffCHAIN BALANCE
chain length spread
low spread = better shift time
high spread = routing + hold riskscan insertion summary
chain balance report
scan DRC log
clocking legality report
Coverage plateau traced to non-scan flops in reset islands; RTL + DFT lint policy fixed root cause.
Check scan replacement first
Audit chain legality by domain
Validate shift/capture clocks
Ask: what evidence proves this DFT decision is safe for production?
State metric, lot/corner context, and pattern tag with every claim.
Treat timing, power, and quality as one signoff problem.
Chasing coverage without legality checks.
Ignoring test-power side effects of pattern changes.
Debugging silicon without reproducible tags.
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