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Course contents

  • How to Use This Course
  • DFT Metrics Reference
  • DFT Glossary
  • Reading Path
  • Scan Fundamentals61
    • Scan Cell Architecture
    • Chain Stitching Rules
    • Clocking for Test
    • Scan-Ready RTL
      • Scan-Ready RTL: Mechanism
      • Scan-Ready RTL: Inputs & Outputs
      • Scan-Ready RTL: Reports & Metrics
      • Scan-Ready RTL: Debug Playbook
      • Scan-Ready RTL: Worked Example
      • Scan-Ready RTL: Pitfalls & Red Flags
      • Scan-Ready RTL: Interview Drills
      • Scan-Ready RTL: Review Checklist
      • Scan-Ready RTL: Theory Deep Dive
      • Scan-Ready RTL: Design Space
      • Scan-Ready RTL: Expanded Case Study
      • Scan-Ready RTL: Step-by-Step Walkthrough
      • Scan-Ready RTL: Comparison Matrix
      • Scan-Ready RTL: Software / Programmer View
      • Scan-Ready RTL: Silicon PPA Impact
    • Scan Fundamentals: Tricky Q&A
  • Compression & Diagnosis61
  • ATPG & Pattern Generation61
  • MBIST & LBIST61
  • Boundary Scan & JTAG61
  • Test Timing & Power61
  • DFT Physical Integration61
  • DFT Interview Prep61
  • DFT / ATPG Cheatsheet
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‹Scan-Ready RTL
  1. Topics
  2. Design for Test
  3. Scan Fundamentals
  4. Scan-Ready RTL
  5. Scan-Ready RTL: Reports & Metrics

DFT / ATPG · All levels

Scan-Ready RTL: Reports & Metrics

Reports & Metrics for Scan-Ready RTL.

On this page

    Reports and metrics

    Reports & Metrics for Scan-Ready RTL focuses on DFT lint pass rate, uncontrollable register count, black-box scan escapes. The goal is to convert metric movement into mechanism, owner, and release decision.

    A report should support a release decision for DFT lint pass rate, uncontrollable register count, black-box scan escapes. One headline number is rarely enough without setup tags and bucket-level evidence.

    Metric movement

    Diagram
    METRIC GRAPH - DFT lint pass rate, uncontrollable register count, black-box scan escapes
    
    quality metric
      ^
      |                         target
      |                       - - - - - - -
      |                  o after fix + regression
      |              o
      |         o baseline
      |    o regressed run
      +--------------------------------------> closure iteration
        input audit     focused fix      signoff review
    
    Readout:
      - explain what moved, why it moved, and who approved it

    Distribution view

    Diagram
    PATTERN HISTOGRAM - Scan-Ready RTL
    
    pattern count
      |      ***
      |    *******
      |  ***********
      |*************  <- high-volume tail (optimize here)
      +--------------------> pattern buckets
       smoke  stuck-at  transition  diagnosis
    
    Balance quality and tester limits together.
    • Track DFT lint pass rate, uncontrollable register count, black-box scan escapes by context and pattern class.

    • Review trend and bucket detail together.

    • Keep quality, timing, and power metrics in one dashboard.

    • Store each metric next to the artifact and run tag.

    DFT deep dive

    Scan architecture quality determines whether ATPG can control and observe real silicon state.

    Concept diagram

    Diagram
    SCAN INSERTION FLOW
    
    scan-ready RTL -> scan replacement -> stitch chains -> DRC -> ATPG handoff

    Metric graph

    Diagram
    CHAIN BALANCE
    
    chain length spread
    low spread   = better shift time
    high spread  = routing + hold risk

    Reports and artifacts

    • scan insertion summary

    • chain balance report

    • scan DRC log

    • clocking legality report

    Mini case study

    Coverage plateau traced to non-scan flops in reset islands; RTL + DFT lint policy fixed root cause.

    Debug branches

    • Check scan replacement first

    • Audit chain legality by domain

    • Validate shift/capture clocks

    Senior review question

    Ask: what evidence proves this DFT decision is safe for production?

    Key takeaways

    • State metric, lot/corner context, and pattern tag with every claim.

    • Treat timing, power, and quality as one signoff problem.

    Common pitfalls

    • Chasing coverage without legality checks.

    • Ignoring test-power side effects of pattern changes.

    • Debugging silicon without reproducible tags.

    Reading reports

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    See also

    • Scan-Ready RTL: Mechanism
    • Scan-Ready RTL: Worked Example
    • Scan-Ready RTL: Pitfalls & Red Flags