Scan-Ready RTL: Theory Deep Dive

Foundational theory

Scan-Ready RTL is central to Scan Fundamentals. RTL coding style controls scanability through reset style, clock gating discipline, and avoiding structures that block controllability/observability. Senior DFT engineers tie metric movement to architecture assumptions, constraints, and silicon evidence rather than isolated tool output.

Core concepts explained

• RTL coding style controls scanability through reset style, clock gating discipline, and avoiding structures that block controllability/observability.

• Primary metric: DFT lint pass rate, uncontrollable register count, black-box scan escapes

• Primary artifact: DFT lint report, non-scan element list, waiver manifest

• Owners: RTL owner, DFT owner, verification owner

• Controllability and observability must be explicit

• Production-quality requires reproducible pattern and tester tags

Why this matters at release

At release, Scan-Ready RTL issues can create coverage escapes, unstable production bins, or long debug loops. Scan architecture determines controllability and observability quality.

Mental model

scan-ready RTL -> scan insertion -> stitch -> DRC -> ATPG handoff

Worked intuition

1. Name failing metric and scenario context (mode, lot/corner, program).

2. Open DFT lint pass rate, uncontrollable register count, black-box scan escapes trend and isolate dominant failing bucket.

3. Trace architecture assumptions and legality constraints.

4. Check compression, clocking, and unknown handling dependencies.

5. Collect DFT lint report, non-scan element list, waiver manifest and confirm run tags.

6. Classify issue: model/constraint, physical/test setup, or real defect signal.

7. Propose minimal fix and list timing/power/quality regression checks.

Common misconceptions

• Coverage percent alone proves release readiness.

• More compression always means better outcome.

• Silicon mismatch can be debugged without pattern/tester traceability.

• Shift timing and test power can be signed independently.

Visual reinforcement

Scan insertion flow

scan-ready RTL -> scan insertion -> stitch -> DRC -> ATPG handoff

Layer responsibilities

DFT OWNERSHIP LAYERS - Scan-Ready RTL

layer              owns                         failure mode
----------------   --------------------------   -------------------------
rtl/architecture   scanability hooks            uncontrollable logic
atpg/constraints   legal pattern intent         aborts, low coverage
physical/clocking  chain route + test clocks    shift hold/timing escapes
tester/program     pattern apply integrity      false binning / bad fails
quality signoff    release criteria             escapes or schedule slip

DFT deep dive

Scan architecture quality determines whether ATPG can control and observe real silicon state.

Concept diagram

SCAN INSERTION FLOW

scan-ready RTL -> scan replacement -> stitch chains -> DRC -> ATPG handoff

Metric graph

CHAIN BALANCE

chain length spread
low spread   = better shift time
high spread  = routing + hold risk

Reports and artifacts

• scan insertion summary

• chain balance report

• scan DRC log

• clocking legality report

Mini case study

Coverage plateau traced to non-scan flops in reset islands; RTL + DFT lint policy fixed root cause.

Debug branches

• Check scan replacement first

• Audit chain legality by domain

• Validate shift/capture clocks

Senior review question

Ask: what evidence proves this DFT decision is safe for production?

Key takeaways

• State metric, lot/corner context, and pattern tag with every claim.

• Treat timing, power, and quality as one signoff problem.

Common pitfalls

• Chasing coverage without legality checks.

• Ignoring test-power side effects of pattern changes.

• Debugging silicon without reproducible tags.

Theory reinforcement

Scan architecture determines controllability and observability quality.