Extended case study

Release review: test clock reachability, pulse legality, scan shift/capture violations regresses after a test-flow update touching Clocking for Test.

Background

Team had prior signoff, then a new program/config introduced regressions in selected buckets.

Symptoms observed

• test clock reachability, pulse legality, scan shift/capture violations regression

• Mismatch between simulation and tester

• Escalation without clear owner

Investigation timeline

1. Hour 0: freeze pattern set, constraints, and tester program tags

2. Hour 1: isolate first failing bucket by mode/lot

3. Hour 2: verify legality and constraints assumptions

4. Hour 3: correlate with physical/timing/power context

5. Hour 4: choose minimal reversible fix

6. Hour 5: run full signoff regression matrix

7. Hour 6: publish decision memo and owners

Root cause

Root cause tied to Clocking for Test: Test clocks must safely drive scan shift and at-speed capture modes without violating clock gating, pulse width, or domain assumptions.

Fix and validation

• Apply bounded fix with owner

• Re-run test clock tree report, pulse check report, ATPG clock constraints

• Re-validate quality, timing, and test power

Lessons learned

• Tag every run artifact

• Mechanism first, command second

• Close with explicit release decision

CASE STUDY - Clocking for Test
baseline metric / regressed metric / post-fix metric

Sequence under stress

DFT FLOW - Clocking for Test

scan insertion -> chain stitch -> compression map -> ATPG -> tester apply -> diagnosis
      |                |                |            |             |
 controllability   shift balance    channel use   coverage     silicon correlation

Primary metric: test clock reachability, pulse legality, scan shift/capture violations

DFT deep dive

Scan architecture quality determines whether ATPG can control and observe real silicon state.

Concept diagram

SCAN INSERTION FLOW

scan-ready RTL -> scan replacement -> stitch chains -> DRC -> ATPG handoff

Metric graph

CHAIN BALANCE

chain length spread
low spread   = better shift time
high spread  = routing + hold risk

Reports and artifacts

• scan insertion summary

• chain balance report

• scan DRC log

• clocking legality report

Mini case study

Coverage plateau traced to non-scan flops in reset islands; RTL + DFT lint policy fixed root cause.

Debug branches

• Check scan replacement first

• Audit chain legality by domain

• Validate shift/capture clocks

Senior review question

Ask: what evidence proves this DFT decision is safe for production?

Key takeaways

• State metric, lot/corner context, and pattern tag with every claim.

• Treat timing, power, and quality as one signoff problem.

Common pitfalls

• Chasing coverage without legality checks.

• Ignoring test-power side effects of pattern changes.

• Debugging silicon without reproducible tags.

Principal DFT review addendum

Test clocks must safely drive scan shift and at-speed capture modes without violating clock gating, pulse width, or domain assumptions.

Metric: test clock reachability, pulse legality, scan shift/capture violations