Review Checklist for Clocking for Test focuses on test clock reachability, pulse legality, scan shift/capture violations. The goal is to convert metric movement into mechanism, owner, and release decision.
Run tags and scenario context are explicit.
Constraints and legality assumptions are documented.
Quality, timing, and test-power checks are included.
Diagnosis evidence supports residual-risk decision.
Owners signed: DFT owner, CTS owner, STA owner.
OWNERSHIP MAP - Clocking for Test
artifact owner
---------------- -----------------
architecture/report DFT owner
constraints/setup CTS owner
physical/test STA owner
Name an owner for each failing metric cluster.Scan architecture quality determines whether ATPG can control and observe real silicon state.
SCAN INSERTION FLOW
scan-ready RTL -> scan replacement -> stitch chains -> DRC -> ATPG handoffCHAIN BALANCE
chain length spread
low spread = better shift time
high spread = routing + hold riskscan insertion summary
chain balance report
scan DRC log
clocking legality report
Coverage plateau traced to non-scan flops in reset islands; RTL + DFT lint policy fixed root cause.
Check scan replacement first
Audit chain legality by domain
Validate shift/capture clocks
Ask: what evidence proves this DFT decision is safe for production?
State metric, lot/corner context, and pattern tag with every claim.
Treat timing, power, and quality as one signoff problem.
Chasing coverage without legality checks.
Ignoring test-power side effects of pattern changes.
Debugging silicon without reproducible tags.
Test clocks must safely drive scan shift and at-speed capture modes without violating clock gating, pulse width, or domain assumptions.
Metric: test clock reachability, pulse legality, scan shift/capture violations
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