Clocking for Test: Mechanism

Mechanism to understand

Mechanism for Clocking for Test focuses on test clock reachability, pulse legality, scan shift/capture violations. The goal is to convert metric movement into mechanism, owner, and release decision.

Test clocks must safely drive scan shift and at-speed capture modes without violating clock gating, pulse width, or domain assumptions. Think of DFT as a quality pipeline where setup quality determines what silicon evidence means.

• Identify where controllability/observability is introduced.

• Identify legal constraints and mode assumptions.

• Identify failure class: architecture, constraints, physical, or silicon.

Layered view

DFT CLOSURE FLOW - Clocking for Test

scan/test architecture
        |
        v
ATPG constraints + fault models
        |
        v
pattern generation + compression
        |
        v
timing/power/physical validation
        |
        v
silicon diagnosis and release signoff

Debug rule: always state metric, run tags, and owning team with any claim.

Shift vs capture clocking

TEST CLOCK MODES

shift:   many low-frequency pulses (hold-sensitive)
capture: one/few at-speed pulses (setup-sensitive)

same chain, different timing risk profile.

Layer responsibilities

DFT OWNERSHIP LAYERS - Clocking for Test

layer              owns                         failure mode
----------------   --------------------------   -------------------------
rtl/architecture   scanability hooks            uncontrollable logic
atpg/constraints   legal pattern intent         aborts, low coverage
physical/clocking  chain route + test clocks    shift hold/timing escapes
tester/program     pattern apply integrity      false binning / bad fails
quality signoff    release criteria             escapes or schedule slip

DFT deep dive

Scan architecture quality determines whether ATPG can control and observe real silicon state.

Concept diagram

SCAN INSERTION FLOW

scan-ready RTL -> scan replacement -> stitch chains -> DRC -> ATPG handoff

Metric graph

CHAIN BALANCE

chain length spread
low spread   = better shift time
high spread  = routing + hold risk

Reports and artifacts

• scan insertion summary

• chain balance report

• scan DRC log

• clocking legality report

Mini case study

Coverage plateau traced to non-scan flops in reset islands; RTL + DFT lint policy fixed root cause.

Debug branches

• Check scan replacement first

• Audit chain legality by domain

• Validate shift/capture clocks

Senior review question

Ask: what evidence proves this DFT decision is safe for production?

Key takeaways

• State metric, lot/corner context, and pattern tag with every claim.

• Treat timing, power, and quality as one signoff problem.

Common pitfalls

• Chasing coverage without legality checks.

• Ignoring test-power side effects of pattern changes.

• Debugging silicon without reproducible tags.

Mechanism deep dive

Test clocks must safely drive scan shift and at-speed capture modes without violating clock gating, pulse width, or domain assumptions.