Scan decisions trade shift time, routing burden, and debug clarity.
+------------------+----------------+----------------+----------------+
| Approach | Strength | Weakness | Best when |
+------------------+----------------+----------------+----------------+
| Conservative | safe | higher cost | ramp-sensitive |
| Balanced | practical | needs rigor | production |
| Aggressive | fast | escape risk | schedule pressure |
| Architecture | durable | slow | repeated pain |
+------------------+----------------+----------------+----------------+Tie approach to product risk and tester constraints
Optimizing one metric only
No regression ownership
DFT EVIDENCE MATRIX - Clocking for Test
+-------------------+------------------------+--------------------------+-------------------------+
| Evidence | Tells you | Does not prove | Next action |
+-------------------+------------------------+--------------------------+-------------------------+
| coverage report | fault detect trends | silicon root cause | inspect bucket details |
| pattern diff | generation changes | architecture quality | replay suspect patterns |
| timing/power report| test closure margin | diagnosis confidence | correlate fail logs |
| diagnosis summary | likely defect classes | ownership decision | assign action owner |
| signoff checklist | process completeness | correctness of evidence | peer review artifacts |
+-------------------+------------------------+--------------------------+-------------------------+Scan architecture quality determines whether ATPG can control and observe real silicon state.
SCAN INSERTION FLOW
scan-ready RTL -> scan replacement -> stitch chains -> DRC -> ATPG handoffCHAIN BALANCE
chain length spread
low spread = better shift time
high spread = routing + hold riskscan insertion summary
chain balance report
scan DRC log
clocking legality report
Coverage plateau traced to non-scan flops in reset islands; RTL + DFT lint policy fixed root cause.
Check scan replacement first
Audit chain legality by domain
Validate shift/capture clocks
Ask: what evidence proves this DFT decision is safe for production?
State metric, lot/corner context, and pattern tag with every claim.
Treat timing, power, and quality as one signoff problem.
Chasing coverage without legality checks.
Ignoring test-power side effects of pattern changes.
Debugging silicon without reproducible tags.
Test clocks must safely drive scan shift and at-speed capture modes without violating clock gating, pulse width, or domain assumptions.
Metric: test clock reachability, pulse legality, scan shift/capture violations
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