Step-by-step analysis walkthrough

Use when you own Clocking for Test in a DFT closure review.

1. Open release criteria and failing metric dashboard.

2. Partition failures by pattern family and operating context.

3. Inspect constraints, clocks, masks, and unknown handling.

4. Check architecture assumptions against implementation reality.

5. Review diagnosis evidence for repeatability.

6. Assign owner and propose smallest high-confidence change.

7. Run timing, power, and quality regressions.

8. Capture final signoff or waiver decision.

Artifacts to collect

• test clock tree report, pulse check report, ATPG clock constraints

• pattern tag manifest

• tester program revision

• signoff checklist

• owner tracker

Decision memo template

DFT DECISION MEMO - Clocking for Test
scenario:
metric:
hypothesis:
fix:
regression:
owners: DFT owner, CTS owner, STA owner

Reference visuals

Shift vs capture clocking

TEST CLOCK MODES

shift:   many low-frequency pulses (hold-sensitive)
capture: one/few at-speed pulses (setup-sensitive)

same chain, different timing risk profile.

DFT deep dive

Scan architecture quality determines whether ATPG can control and observe real silicon state.

Concept diagram

SCAN INSERTION FLOW

scan-ready RTL -> scan replacement -> stitch chains -> DRC -> ATPG handoff

Metric graph

CHAIN BALANCE

chain length spread
low spread   = better shift time
high spread  = routing + hold risk

Reports and artifacts

• scan insertion summary

• chain balance report

• scan DRC log

• clocking legality report

Mini case study

Coverage plateau traced to non-scan flops in reset islands; RTL + DFT lint policy fixed root cause.

Debug branches

• Check scan replacement first

• Audit chain legality by domain

• Validate shift/capture clocks

Senior review question

Ask: what evidence proves this DFT decision is safe for production?

Key takeaways

• State metric, lot/corner context, and pattern tag with every claim.

• Treat timing, power, and quality as one signoff problem.

Common pitfalls

• Chasing coverage without legality checks.

• Ignoring test-power side effects of pattern changes.

• Debugging silicon without reproducible tags.

Principal DFT review addendum

Test clocks must safely drive scan shift and at-speed capture modes without violating clock gating, pulse width, or domain assumptions.

Metric: test clock reachability, pulse legality, scan shift/capture violations