Clocking for Test: Worked Example

Worked example

Worked Example for Clocking for Test focuses on test clock reachability, pulse legality, scan shift/capture violations. The goal is to convert metric movement into mechanism, owner, and release decision.

A release review shows regression on test clock reachability, pulse legality, scan shift/capture violations. The strongest first move is to freeze evidence, isolate one failing bucket, and prove mechanism before changing flow knobs.

Sequence under inspection

DFT FLOW - Clocking for Test

scan insertion -> chain stitch -> compression map -> ATPG -> tester apply -> diagnosis
      |                |                |            |             |
 controllability   shift balance    channel use   coverage     silicon correlation

Primary metric: test clock reachability, pulse legality, scan shift/capture violations

Shift vs capture clocking

TEST CLOCK MODES

shift:   many low-frequency pulses (hold-sensitive)
capture: one/few at-speed pulses (setup-sensitive)

same chain, different timing risk profile.

1. Capture failing report and exact run tags.

2. Tag scenario (mode, lot/corner, pattern class).

3. Trace first dependency that changed.

4. Compare against test clock tree report, pulse check report, ATPG clock constraints.

5. Choose one reversible fix and predefine regression checks.

Did the fix work?

BEFORE / AFTER - Clocking for Test

metric quality
  ^
  |                    --- release target
  |      o regressed
  |           o baseline
  |                o after fix
  +-------------------------------> closure iteration

Prove quality, timing, and test-power all moved safely.

DFT deep dive

Scan architecture quality determines whether ATPG can control and observe real silicon state.

Concept diagram

SCAN INSERTION FLOW

scan-ready RTL -> scan replacement -> stitch chains -> DRC -> ATPG handoff

Metric graph

CHAIN BALANCE

chain length spread
low spread   = better shift time
high spread  = routing + hold risk

Reports and artifacts

• scan insertion summary

• chain balance report

• scan DRC log

• clocking legality report

Mini case study

Coverage plateau traced to non-scan flops in reset islands; RTL + DFT lint policy fixed root cause.

Debug branches

• Check scan replacement first

• Audit chain legality by domain

• Validate shift/capture clocks

Senior review question

Ask: what evidence proves this DFT decision is safe for production?

Key takeaways

• State metric, lot/corner context, and pattern tag with every claim.

• Treat timing, power, and quality as one signoff problem.

Common pitfalls

• Chasing coverage without legality checks.

• Ignoring test-power side effects of pattern changes.

• Debugging silicon without reproducible tags.

Principal DFT review addendum

Test clocks must safely drive scan shift and at-speed capture modes without violating clock gating, pulse width, or domain assumptions.

Metric: test clock reachability, pulse legality, scan shift/capture violations