Clocking for Test: Reports & Metrics

Reports and metrics

Reports & Metrics for Clocking for Test focuses on test clock reachability, pulse legality, scan shift/capture violations. The goal is to convert metric movement into mechanism, owner, and release decision.

A report should support a release decision for test clock reachability, pulse legality, scan shift/capture violations. One headline number is rarely enough without setup tags and bucket-level evidence.

Metric movement

METRIC GRAPH - test clock reachability, pulse legality, scan shift/capture violations

quality metric
  ^
  |                         target
  |                       - - - - - - -
  |                  o after fix + regression
  |              o
  |         o baseline
  |    o regressed run
  +--------------------------------------> closure iteration
    input audit     focused fix      signoff review

Readout:
  - explain what moved, why it moved, and who approved it

Distribution view

PATTERN HISTOGRAM - Clocking for Test

pattern count
  |      ***
  |    *******
  |  ***********
  |*************  <- high-volume tail (optimize here)
  +--------------------> pattern buckets
   smoke  stuck-at  transition  diagnosis

Balance quality and tester limits together.

• Track test clock reachability, pulse legality, scan shift/capture violations by context and pattern class.

• Review trend and bucket detail together.

• Keep quality, timing, and power metrics in one dashboard.

• Store each metric next to the artifact and run tag.

DFT deep dive

Scan architecture quality determines whether ATPG can control and observe real silicon state.

Concept diagram

SCAN INSERTION FLOW

scan-ready RTL -> scan replacement -> stitch chains -> DRC -> ATPG handoff

Metric graph

CHAIN BALANCE

chain length spread
low spread   = better shift time
high spread  = routing + hold risk

Reports and artifacts

• scan insertion summary

• chain balance report

• scan DRC log

• clocking legality report

Mini case study

Coverage plateau traced to non-scan flops in reset islands; RTL + DFT lint policy fixed root cause.

Debug branches

• Check scan replacement first

• Audit chain legality by domain

• Validate shift/capture clocks

Senior review question

Ask: what evidence proves this DFT decision is safe for production?

Key takeaways

• State metric, lot/corner context, and pattern tag with every claim.

• Treat timing, power, and quality as one signoff problem.

Common pitfalls

• Chasing coverage without legality checks.

• Ignoring test-power side effects of pattern changes.

• Debugging silicon without reproducible tags.

Reading reports