Clocking for Test: Interview Drills

Interview drills

Interview Drills for Clocking for Test focuses on test clock reachability, pulse legality, scan shift/capture violations. The goal is to convert metric movement into mechanism, owner, and release decision.

PROMPT
You observe test clock reachability, pulse legality, scan shift/capture violations on Clocking for Test. Walk through diagnosis and release decision.

STRONG ANSWER
1. States context and run tags.
2. Explains mechanism: Test clocks must safely drive scan shift and at-speed capture modes without violating clock gating, pulse width, or domain assumptions.
3. Requests test clock tree report, pulse check report, ATPG clock constraints.
4. Proposes minimal fix and regression.

WEAK ANSWER
Jumps to tool switches without evidence quality, ownership, or regression plan.

Diagram to draw on the whiteboard

Shift vs capture clocking

TEST CLOCK MODES

shift:   many low-frequency pulses (hold-sensitive)
capture: one/few at-speed pulses (setup-sensitive)

same chain, different timing risk profile.

Root-cause narrative

ROOT-CAUSE TREE - Clocking for Test

test clock reachability, pulse legality, scan shift/capture violations regresses
        |
  setup changed?
    /        \
  yes         no
  |            |
constraint    silicon or
or ATPG       physical/test path
 /    \          |
SDC   model    chain/clock/power/diagnosis
diff  diff     isolate first failing signature

DFT deep dive

Scan architecture quality determines whether ATPG can control and observe real silicon state.

Concept diagram

SCAN INSERTION FLOW

scan-ready RTL -> scan replacement -> stitch chains -> DRC -> ATPG handoff

Metric graph

CHAIN BALANCE

chain length spread
low spread   = better shift time
high spread  = routing + hold risk

Reports and artifacts

• scan insertion summary

• chain balance report

• scan DRC log

• clocking legality report

Mini case study

Coverage plateau traced to non-scan flops in reset islands; RTL + DFT lint policy fixed root cause.

Debug branches

• Check scan replacement first

• Audit chain legality by domain

• Validate shift/capture clocks

Senior review question

Ask: what evidence proves this DFT decision is safe for production?

Key takeaways

• State metric, lot/corner context, and pattern tag with every claim.

• Treat timing, power, and quality as one signoff problem.

Common pitfalls

• Chasing coverage without legality checks.

• Ignoring test-power side effects of pattern changes.

• Debugging silicon without reproducible tags.

Principal DFT review addendum

Test clocks must safely drive scan shift and at-speed capture modes without violating clock gating, pulse width, or domain assumptions.

Metric: test clock reachability, pulse legality, scan shift/capture violations