Clocking for Test: Design Space

Design space exploration

For Clocking for Test, release options trade quality, tester cost, and schedule risk.

Option A - conservative

• Conservative quality: helps debug confidence

• Risk: higher test cost

• Validate with: first production ramps

Option B - balanced

• Balanced release: helps quality and cost

• Risk: needs discipline

• Validate with: mainstream products

Option C - aggressive

• Aggressive schedule: helps faster closure

• Risk: escape risk

• Validate with: late tapeout pressure

Option D - architecture change

• Architecture change: helps long-term quality

• Risk: schedule hit

• Validate with: chronic recurring failures

DESIGN SPACE - Clocking for Test
quality <-> tester cost <-> schedule

Design pitfalls

• No ownership for quality gap

• Fixing one metric while regressing another

Tradeoff curve

BEFORE / AFTER - Clocking for Test

metric quality
  ^
  |                    --- release target
  |      o regressed
  |           o baseline
  |                o after fix
  +-------------------------------> closure iteration

Prove quality, timing, and test-power all moved safely.

DFT deep dive

Scan architecture quality determines whether ATPG can control and observe real silicon state.

Concept diagram

SCAN INSERTION FLOW

scan-ready RTL -> scan replacement -> stitch chains -> DRC -> ATPG handoff

Metric graph

CHAIN BALANCE

chain length spread
low spread   = better shift time
high spread  = routing + hold risk

Reports and artifacts

• scan insertion summary

• chain balance report

• scan DRC log

• clocking legality report

Mini case study

Coverage plateau traced to non-scan flops in reset islands; RTL + DFT lint policy fixed root cause.

Debug branches

• Check scan replacement first

• Audit chain legality by domain

• Validate shift/capture clocks

Senior review question

Ask: what evidence proves this DFT decision is safe for production?

Key takeaways

• State metric, lot/corner context, and pattern tag with every claim.

• Treat timing, power, and quality as one signoff problem.

Common pitfalls

• Chasing coverage without legality checks.

• Ignoring test-power side effects of pattern changes.

• Debugging silicon without reproducible tags.

Principal DFT review addendum

Test clocks must safely drive scan shift and at-speed capture modes without violating clock gating, pulse width, or domain assumptions.

Metric: test clock reachability, pulse legality, scan shift/capture violations