Interview drills

Interview Drills for Scan Chain Physical Effects focuses on scan wirelength, congestion from chain ordering, hold buffer overhead. The goal is to convert metric movement into mechanism, owner, and release decision.

PROMPT
You observe scan wirelength, congestion from chain ordering, hold buffer overhead on Scan Chain Physical Effects. Walk through diagnosis and release decision.

STRONG ANSWER
1. States context and run tags.
2. Explains mechanism: Logical chain order interacts with placement and routing; poor ordering inflates wirelength, congestion, and shift hold fixes.
3. Requests scan physical report, wirelength histogram, congestion heatmap.
4. Proposes minimal fix and regression.

WEAK ANSWER
Jumps to tool switches without evidence quality, ownership, or regression plan.

Diagram to draw on the whiteboard

Physical chain consequences

chain order -> wirelength -> congestion -> hold buffers -> shift timing risk

Root-cause narrative

ROOT-CAUSE TREE - Scan Chain Physical Effects

scan wirelength, congestion from chain ordering, hold buffer overhead regresses
        |
  setup changed?
    /        \
  yes         no
  |            |
constraint    silicon or
or ATPG       physical/test path
 /    \          |
SDC   model    chain/clock/power/diagnosis
diff  diff     isolate first failing signature

DFT deep dive

Physical integration quality decides whether DFT architecture survives implementation realities.

Concept diagram

PHYSICAL DFT FLOW

chain planning -> floorplan placement -> route -> test timing/power validation

Metric graph

ROUTING BURDEN

poor chain order -> longer routes -> more hold buffers

Reports and artifacts

• scan physical wirelength

• congestion heatmap

• test clock skew

• handoff issue tracker

Mini case study

Late scan reorder reduced route detours and eliminated a major shift hold cluster before signoff.

Debug branches

• Correlate chain order with congestion

• Place compression logic near chain clusters

• Keep DFT-PD handoff versioned

Senior review question

Ask: what evidence proves this DFT decision is safe for production?

Key takeaways

• State metric, lot/corner context, and pattern tag with every claim.

• Treat timing, power, and quality as one signoff problem.

Common pitfalls

• Chasing coverage without legality checks.

• Ignoring test-power side effects of pattern changes.

• Debugging silicon without reproducible tags.

Principal DFT review addendum

Logical chain order interacts with placement and routing; poor ordering inflates wirelength, congestion, and shift hold fixes.

Metric: scan wirelength, congestion from chain ordering, hold buffer overhead