Package Test Interface: Debug Playbook

Debug playbook

Debug Playbook for Package Test Interface focuses on pin mux correctness, package test mode coverage, board bring-up escape count. The goal is to convert metric movement into mechanism, owner, and release decision.

Debug aims to find the first incorrect assumption, not the loudest downstream symptom. Start with reproducibility and ownership.

Root-cause tree

ROOT-CAUSE TREE - Package Test Interface

pin mux correctness, package test mode coverage, board bring-up escape count regresses
        |
  setup changed?
    /        \
  yes         no
  |            |
constraint    silicon or
or ATPG       physical/test path
 /    \          |
SDC   model    chain/clock/power/diagnosis
diff  diff     isolate first failing signature

1. Freeze run tags for patterns, constraints, and tester setup.

2. Isolate first failing metric bucket and scenario.

3. Classify failure source: model, constraints, physical, or silicon.

4. Prove mechanism with one reduced replay or targeted run.

5. Apply smallest owner-controlled fix.

6. Re-run timing, power, and quality regression matrix.

Review memo template

STAFF DFT REVIEW MEMO - Boundary Scan & JTAG / Package Test Interface

1. Symptom
   - Watched metric: pin mux correctness, package test mode coverage, board bring-up escape count
   - Failing scenario: <mode/lot/corner/program>
   - Pattern class: <scan/transition/compressed/BIST/JTAG>
   - Tags: <constraints, patterns, tester program, netlist>

2. Mechanism hypothesis
   - Primary mechanism: Package and board interfaces determine whether intended boundary and test modes can be exercised without conflicting with functional muxing.
   - Competing hypothesis: <constraint issue, model issue, physical issue, silicon issue>
   - Missing evidence: <report, replay, diagnosis trace>

3. Proposed action
   - Minimal reversible change: <constraint fix, architecture tweak, pattern update>
   - Expected metric movement: <delta>
   - Regression risk: timing, power, quality, schedule

4. Signoff
   - Re-run artifact: package pinmux table, board test checklist, interface validation report
   - Required owners: package owner, board owner, DFT lead
   - Final decision: release, waive, rollback, or escalate

DFT deep dive

Boundary scan and JTAG are board-level contracts, not just RTL features.

Concept diagram

JTAG ACCESS

TAP controller -> instruction register -> boundary/data register -> board test/debug

Metric graph

BOARD TEST READINESS

instruction coverage vs pin controllability

Reports and artifacts

• TAP compliance report

• boundary cell coverage matrix

• EXTEST/INTEST results

• debug lock policy log

Mini case study

Board bring-up blocked by pinmux override in one mode; TAP instruction decode and package table alignment fixed path.

Debug branches

• Verify TAP state transitions

• Audit package pin ownership

• Check security lifecycle lock behavior

Senior review question

Ask: what evidence proves this DFT decision is safe for production?

Key takeaways

• State metric, lot/corner context, and pattern tag with every claim.

• Treat timing, power, and quality as one signoff problem.

Common pitfalls

• Chasing coverage without legality checks.

• Ignoring test-power side effects of pattern changes.

• Debugging silicon without reproducible tags.

Principal DFT review addendum

Package and board interfaces determine whether intended boundary and test modes can be exercised without conflicting with functional muxing.

Metric: pin mux correctness, package test mode coverage, board bring-up escape count