DenseChip

DFT / ATPG · All levels

Debug Access Port: Expanded Case Study

Expanded Case Study for Debug Access Port.

Extended case study

Release review: debug access latency, security lock compliance, bring-up access reliability regresses after a test-flow update touching Debug Access Port.

Background

Team had prior signoff, then a new program/config introduced regressions in selected buckets.

Symptoms observed

  • debug access latency, security lock compliance, bring-up access reliability regression

  • Mismatch between simulation and tester

  • Escalation without clear owner

Investigation timeline

  1. Hour 0: freeze pattern set, constraints, and tester program tags

  2. Hour 1: isolate first failing bucket by mode/lot

  3. Hour 2: verify legality and constraints assumptions

  4. Hour 3: correlate with physical/timing/power context

  5. Hour 4: choose minimal reversible fix

  6. Hour 5: run full signoff regression matrix

  7. Hour 6: publish decision memo and owners

Root cause

Root cause tied to Debug Access Port: Debug access over JTAG must balance bring-up visibility with production security and lifecycle lock policy.

Fix and validation

  • Apply bounded fix with owner

  • Re-run debug access policy, lock/unlock flow, bring-up access logs

  • Re-validate quality, timing, and test power

Lessons learned

  • Tag every run artifact

  • Mechanism first, command second

  • Close with explicit release decision

diagram
CASE STUDY - Debug Access Port
baseline metric / regressed metric / post-fix metric

Sequence under stress

diagram
DFT FLOW - Debug Access Port

scan insertion -> chain stitch -> compression map -> ATPG -> tester apply -> diagnosis
      |                |                |            |             |
 controllability   shift balance    channel use   coverage     silicon correlation

Primary metric: debug access latency, security lock compliance, bring-up access reliability

DFT deep dive

Boundary scan and JTAG are board-level contracts, not just RTL features.

Concept diagram

diagram
JTAG ACCESS

TAP controller -> instruction register -> boundary/data register -> board test/debug

Metric graph

diagram
BOARD TEST READINESS

instruction coverage vs pin controllability

Reports and artifacts

  • TAP compliance report

  • boundary cell coverage matrix

  • EXTEST/INTEST results

  • debug lock policy log

Mini case study

Board bring-up blocked by pinmux override in one mode; TAP instruction decode and package table alignment fixed path.

Debug branches

  • Verify TAP state transitions

  • Audit package pin ownership

  • Check security lifecycle lock behavior

Senior review question

Ask: what evidence proves this DFT decision is safe for production?

Key takeaways

  • State metric, lot/corner context, and pattern tag with every claim.

  • Treat timing, power, and quality as one signoff problem.

Common pitfalls

  • Chasing coverage without legality checks.

  • Ignoring test-power side effects of pattern changes.

  • Debugging silicon without reproducible tags.

Principal DFT review addendum

Debug access over JTAG must balance bring-up visibility with production security and lifecycle lock policy.

Metric: debug access latency, security lock compliance, bring-up access reliability

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