Review Checklist for Debug Access Port focuses on debug access latency, security lock compliance, bring-up access reliability. The goal is to convert metric movement into mechanism, owner, and release decision.
Run tags and scenario context are explicit.
Constraints and legality assumptions are documented.
Quality, timing, and test-power checks are included.
Diagnosis evidence supports residual-risk decision.
Owners signed: security owner, bring-up owner, DFT owner.
OWNERSHIP MAP - Debug Access Port
artifact owner
---------------- -----------------
architecture/report security owner
constraints/setup bring-up owner
physical/test DFT owner
Name an owner for each failing metric cluster.Boundary scan and JTAG are board-level contracts, not just RTL features.
JTAG ACCESS
TAP controller -> instruction register -> boundary/data register -> board test/debugBOARD TEST READINESS
instruction coverage vs pin controllabilityTAP compliance report
boundary cell coverage matrix
EXTEST/INTEST results
debug lock policy log
Board bring-up blocked by pinmux override in one mode; TAP instruction decode and package table alignment fixed path.
Verify TAP state transitions
Audit package pin ownership
Check security lifecycle lock behavior
Ask: what evidence proves this DFT decision is safe for production?
State metric, lot/corner context, and pattern tag with every claim.
Treat timing, power, and quality as one signoff problem.
Chasing coverage without legality checks.
Ignoring test-power side effects of pattern changes.
Debugging silicon without reproducible tags.
Debug access over JTAG must balance bring-up visibility with production security and lifecycle lock policy.
Metric: debug access latency, security lock compliance, bring-up access reliability
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