DFT / ATPG · All levels

BIST Signoff: Expanded Case Study

Expanded Case Study for BIST Signoff.

Extended case study

Release review: MBIST/LBIST pass criteria, startup test time, in-field diagnostic readiness regresses after a test-flow update touching BIST Signoff.

Background

Team had prior signoff, then a new program/config introduced regressions in selected buckets.

Symptoms observed

  • MBIST/LBIST pass criteria, startup test time, in-field diagnostic readiness regression

  • Mismatch between simulation and tester

  • Escalation without clear owner

Investigation timeline

  1. Hour 0: freeze pattern set, constraints, and tester program tags

  2. Hour 1: isolate first failing bucket by mode/lot

  3. Hour 2: verify legality and constraints assumptions

  4. Hour 3: correlate with physical/timing/power context

  5. Hour 4: choose minimal reversible fix

  6. Hour 5: run full signoff regression matrix

  7. Hour 6: publish decision memo and owners

Root cause

Root cause tied to BIST Signoff: BIST signoff verifies architecture correctness, quality targets, safety intent, and production programmability before release.

Fix and validation

  • Apply bounded fix with owner

  • Re-run BIST signoff checklist, startup test profile, release approval memo

  • Re-validate quality, timing, and test power

Lessons learned

  • Tag every run artifact

  • Mechanism first, command second

  • Close with explicit release decision

diagram
CASE STUDY - BIST Signoff
baseline metric / regressed metric / post-fix metric

Sequence under stress

diagram
DFT FLOW - BIST Signoff

scan insertion -> chain stitch -> compression map -> ATPG -> tester apply -> diagnosis
      |                |                |            |             |
 controllability   shift balance    channel use   coverage     silicon correlation

Primary metric: MBIST/LBIST pass criteria, startup test time, in-field diagnostic readiness

DFT deep dive

BIST value is realized only when insertion, diagnosis, and repair are tied to production flow.

Concept diagram

diagram
BIST FLOW

insert MBIST/LBIST -> execute -> collect signatures -> diagnose/repair -> signoff

Metric graph

diagram
REPAIR EFFECT

yield
  ^
  |      o pre-repair
  |             o post-repair
  +---------------------> lot

Reports and artifacts

  • MBIST insertion coverage

  • repair signature report

  • LBIST resistant fault list

  • BIST release checklist

Mini case study

Fuse programming mismatch blocked repair activation; corrected bring-up script recovered expected yield uplift.

Debug branches

  • Validate BIST reachability

  • Correlate fail maps to repair signatures

  • Audit in-field boot test budget

Senior review question

Ask: what evidence proves this DFT decision is safe for production?

Key takeaways

  • State metric, lot/corner context, and pattern tag with every claim.

  • Treat timing, power, and quality as one signoff problem.

Common pitfalls

  • Chasing coverage without legality checks.

  • Ignoring test-power side effects of pattern changes.

  • Debugging silicon without reproducible tags.

Principal DFT review addendum

BIST signoff verifies architecture correctness, quality targets, safety intent, and production programmability before release.

Metric: MBIST/LBIST pass criteria, startup test time, in-field diagnostic readiness