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Course contents

  • How to Use This Course
  • DFT Metrics Reference
  • DFT Glossary
  • Reading Path
  • Scan Fundamentals61
  • Compression & Diagnosis61
  • ATPG & Pattern Generation61
  • MBIST & LBIST61
  • Boundary Scan & JTAG61
  • Test Timing & Power61
  • DFT Physical Integration61
    • Scan Chain Physical Effects
    • Test Logic Floorplan
    • DFT-PD Handoff
      • DFT-PD Handoff: Mechanism
      • DFT-PD Handoff: Inputs & Outputs
      • DFT-PD Handoff: Reports & Metrics
      • DFT-PD Handoff: Debug Playbook
      • DFT-PD Handoff: Worked Example
      • DFT-PD Handoff: Pitfalls & Red Flags
      • DFT-PD Handoff: Interview Drills
      • DFT-PD Handoff: Review Checklist
      • DFT-PD Handoff: Theory Deep Dive
      • DFT-PD Handoff: Design Space
      • DFT-PD Handoff: Expanded Case Study
      • DFT-PD Handoff: Step-by-Step Walkthrough
      • DFT-PD Handoff: Comparison Matrix
      • DFT-PD Handoff: Software / Programmer View
      • DFT-PD Handoff: Silicon PPA Impact
    • Physical DFT Debug
    • DFT Physical Integration: Tricky Q&A
  • DFT Interview Prep61
  • DFT / ATPG Cheatsheet
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‹DFT-PD Handoff
  1. Topics
  2. Design for Test
  3. DFT Physical Integration
  4. DFT-PD Handoff
  5. DFT-PD Handoff: Debug Playbook

DFT / ATPG · All levels

DFT-PD Handoff: Debug Playbook

Debug Playbook for DFT-PD Handoff.

On this page

    Debug playbook

    Debug Playbook for DFT-PD Handoff focuses on handoff issue count, late-stage DFT ECO volume, closure turnaround. The goal is to convert metric movement into mechanism, owner, and release decision.

    Debug aims to find the first incorrect assumption, not the loudest downstream symptom. Start with reproducibility and ownership.

    Root-cause tree

    Diagram
    ROOT-CAUSE TREE - DFT-PD Handoff
    
    handoff issue count, late-stage DFT ECO volume, closure turnaround regresses
            |
      setup changed?
        /        \
      yes         no
      |            |
    constraint    silicon or
    or ATPG       physical/test path
     /    \          |
    SDC   model    chain/clock/power/diagnosis
    diff  diff     isolate first failing signature
    1. Freeze run tags for patterns, constraints, and tester setup.

    2. Isolate first failing metric bucket and scenario.

    3. Classify failure source: model, constraints, physical, or silicon.

    4. Prove mechanism with one reduced replay or targeted run.

    5. Apply smallest owner-controlled fix.

    6. Re-run timing, power, and quality regression matrix.

    Review memo template

    Diagram
    STAFF DFT REVIEW MEMO - DFT Physical Integration / DFT-PD Handoff
    
    1. Symptom
       - Watched metric: handoff issue count, late-stage DFT ECO volume, closure turnaround
       - Failing scenario: <mode/lot/corner/program>
       - Pattern class: <scan/transition/compressed/BIST/JTAG>
       - Tags: <constraints, patterns, tester program, netlist>
    
    2. Mechanism hypothesis
       - Primary mechanism: Clear DFT-to-PD contracts for chain rules, test clocks, and legal placement constraints prevent expensive late-stage churn.
       - Competing hypothesis: <constraint issue, model issue, physical issue, silicon issue>
       - Missing evidence: <report, replay, diagnosis trace>
    
    3. Proposed action
       - Minimal reversible change: <constraint fix, architecture tweak, pattern update>
       - Expected metric movement: <delta>
       - Regression risk: timing, power, quality, schedule
    
    4. Signoff
       - Re-run artifact: handoff checklist, chain constraint package, ownership matrix
       - Required owners: DFT lead, PD lead, program manager
       - Final decision: release, waive, rollback, or escalate

    DFT deep dive

    Physical integration quality decides whether DFT architecture survives implementation realities.

    Concept diagram

    Diagram
    PHYSICAL DFT FLOW
    
    chain planning -> floorplan placement -> route -> test timing/power validation

    Metric graph

    Diagram
    ROUTING BURDEN
    
    poor chain order -> longer routes -> more hold buffers

    Reports and artifacts

    • scan physical wirelength

    • congestion heatmap

    • test clock skew

    • handoff issue tracker

    Mini case study

    Late scan reorder reduced route detours and eliminated a major shift hold cluster before signoff.

    Debug branches

    • Correlate chain order with congestion

    • Place compression logic near chain clusters

    • Keep DFT-PD handoff versioned

    Senior review question

    Ask: what evidence proves this DFT decision is safe for production?

    Key takeaways

    • State metric, lot/corner context, and pattern tag with every claim.

    • Treat timing, power, and quality as one signoff problem.

    Common pitfalls

    • Chasing coverage without legality checks.

    • Ignoring test-power side effects of pattern changes.

    • Debugging silicon without reproducible tags.

    Principal DFT review addendum

    Clear DFT-to-PD contracts for chain rules, test clocks, and legal placement constraints prevent expensive late-stage churn.

    Metric: handoff issue count, late-stage DFT ECO volume, closure turnaround

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    See also

    • DFT-PD Handoff: Mechanism
    • DFT-PD Handoff: Inputs & Outputs
    • DFT-PD Handoff: Pitfalls & Red Flags