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Course contents

  • How to Use This Course
  • DFT Metrics Reference
  • DFT Glossary
  • Reading Path
  • Scan Fundamentals61
  • Compression & Diagnosis61
  • ATPG & Pattern Generation61
    • Fault Models
    • ATPG Constraints
      • ATPG Constraints: Mechanism
      • ATPG Constraints: Inputs & Outputs
      • ATPG Constraints: Reports & Metrics
      • ATPG Constraints: Debug Playbook
      • ATPG Constraints: Worked Example
      • ATPG Constraints: Pitfalls & Red Flags
      • ATPG Constraints: Interview Drills
      • ATPG Constraints: Review Checklist
      • ATPG Constraints: Theory Deep Dive
      • ATPG Constraints: Design Space
      • ATPG Constraints: Expanded Case Study
      • ATPG Constraints: Step-by-Step Walkthrough
      • ATPG Constraints: Comparison Matrix
      • ATPG Constraints: Software / Programmer View
      • ATPG Constraints: Silicon PPA Impact
    • Pattern Signoff
    • Coverage Closure
    • ATPG & Pattern Generation: Tricky Q&A
  • MBIST & LBIST61
  • Boundary Scan & JTAG61
  • Test Timing & Power61
  • DFT Physical Integration61
  • DFT Interview Prep61
  • DFT / ATPG Cheatsheet
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‹ATPG Constraints
  1. Topics
  2. Design for Test
  3. ATPG & Pattern Generation
  4. ATPG Constraints
  5. ATPG Constraints: Worked Example

DFT / ATPG · All levels

ATPG Constraints: Worked Example

Worked Example for ATPG Constraints.

On this page

    Worked example

    Worked Example for ATPG Constraints focuses on constraint consistency errors, illegal state count, pattern abort rate. The goal is to convert metric movement into mechanism, owner, and release decision.

    A release review shows regression on constraint consistency errors, illegal state count, pattern abort rate. The strongest first move is to freeze evidence, isolate one failing bucket, and prove mechanism before changing flow knobs.

    Sequence under inspection

    Diagram
    DFT FLOW - ATPG Constraints
    
    scan insertion -> chain stitch -> compression map -> ATPG -> tester apply -> diagnosis
          |                |                |            |             |
     controllability   shift balance    channel use   coverage     silicon correlation
    
    Primary metric: constraint consistency errors, illegal state count, pattern abort rate

    ATPG legality envelope

    Diagram
    constraints define legal test states:
    clocks + resets + masks + test enables + safe unknown handling
    
    invalid envelope -> great-looking but unusable patterns.
    1. Capture failing report and exact run tags.

    2. Tag scenario (mode, lot/corner, pattern class).

    3. Trace first dependency that changed.

    4. Compare against ATPG constraint file, legality checker log, constraint diff report.

    5. Choose one reversible fix and predefine regression checks.

    Did the fix work?

    Diagram
    BEFORE / AFTER - ATPG Constraints
    
    metric quality
      ^
      |                    --- release target
      |      o regressed
      |           o baseline
      |                o after fix
      +-------------------------------> closure iteration
    
    Prove quality, timing, and test-power all moved safely.

    DFT deep dive

    ATPG quality comes from fault model choice plus legal constraints, not raw pattern volume alone.

    Concept diagram

    Diagram
    ATPG FLOW
    
    fault model -> constraints -> generation -> simulation -> coverage closure -> signoff

    Metric graph

    Diagram
    COVERAGE GAP
    
    target coverage
      ^
      |      o before closure
      |          o after fixes
      +---------------------> iteration

    Reports and artifacts

    • fault model coverage

    • untestable class report

    • constraint legality errors

    • pattern signoff memo

    Mini case study

    Transition coverage stalled due to clock constraints mismatch; updated at-speed capture definitions recovered target.

    Debug branches

    • Classify untestable faults

    • Diff ATPG constraints each run

    • Pair coverage with pattern budget

    Senior review question

    Ask: what evidence proves this DFT decision is safe for production?

    Key takeaways

    • State metric, lot/corner context, and pattern tag with every claim.

    • Treat timing, power, and quality as one signoff problem.

    Common pitfalls

    • Chasing coverage without legality checks.

    • Ignoring test-power side effects of pattern changes.

    • Debugging silicon without reproducible tags.

    Principal DFT review addendum

    ATPG constraints encode legal test-mode behavior, clocks, resets, and masks so generated patterns are both executable and meaningful.

    Metric: constraint consistency errors, illegal state count, pattern abort rate

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    See also

    • ATPG Constraints: Mechanism
    • ATPG Constraints: Inputs & Outputs
    • ATPG Constraints: Reports & Metrics