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Course contents

  • How to Use This Course
  • DFT Metrics Reference
  • DFT Glossary
  • Reading Path
  • Scan Fundamentals61
  • Compression & Diagnosis61
  • ATPG & Pattern Generation61
    • Fault Models
    • ATPG Constraints
    • Pattern Signoff
    • Coverage Closure
      • Coverage Closure: Mechanism
      • Coverage Closure: Inputs & Outputs
      • Coverage Closure: Reports & Metrics
      • Coverage Closure: Debug Playbook
      • Coverage Closure: Worked Example
      • Coverage Closure: Pitfalls & Red Flags
      • Coverage Closure: Interview Drills
      • Coverage Closure: Review Checklist
      • Coverage Closure: Theory Deep Dive
      • Coverage Closure: Design Space
      • Coverage Closure: Expanded Case Study
      • Coverage Closure: Step-by-Step Walkthrough
      • Coverage Closure: Comparison Matrix
      • Coverage Closure: Software / Programmer View
      • Coverage Closure: Silicon PPA Impact
    • ATPG & Pattern Generation: Tricky Q&A
  • MBIST & LBIST61
  • Boundary Scan & JTAG61
  • Test Timing & Power61
  • DFT Physical Integration61
  • DFT Interview Prep61
  • DFT / ATPG Cheatsheet
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‹Coverage Closure
  1. Topics
  2. Design for Test
  3. ATPG & Pattern Generation
  4. Coverage Closure
  5. Coverage Closure: Theory Deep Dive

DFT / ATPG · All levels

Coverage Closure: Theory Deep Dive

Theory Deep Dive for Coverage Closure.

On this page

    Foundational theory

    Coverage Closure is central to ATPG & Pattern Generation. Coverage closure uses targeted analysis of undetected faults, constraints, and design-for-test hooks to close quality gaps without exploding pattern volume. Senior DFT engineers tie metric movement to architecture assumptions, constraints, and silicon evidence rather than isolated tool output.

    Core concepts explained

    • Coverage closure uses targeted analysis of undetected faults, constraints, and design-for-test hooks to close quality gaps without exploding pattern volume.

    • Primary metric: coverage gap to target, dominant undetected classes, closure iteration count

    • Primary artifact: coverage gap report, undetected fault buckets, closure action tracker

    • Owners: ATPG owner, DFT owner, design owner

    • Controllability and observability must be explicit

    • Production-quality requires reproducible pattern and tester tags

    Why this matters at release

    At release, Coverage Closure issues can create coverage escapes, unstable production bins, or long debug loops. ATPG is a model-driven search constrained by legal test behavior.

    Mental model

    Diagram
    fault models -> constraints -> generation -> coverage closure -> signoff

    Worked intuition

    1. Name failing metric and scenario context (mode, lot/corner, program).

    2. Open coverage gap to target, dominant undetected classes, closure iteration count trend and isolate dominant failing bucket.

    3. Trace architecture assumptions and legality constraints.

    4. Check compression, clocking, and unknown handling dependencies.

    5. Collect coverage gap report, undetected fault buckets, closure action tracker and confirm run tags.

    6. Classify issue: model/constraint, physical/test setup, or real defect signal.

    7. Propose minimal fix and list timing/power/quality regression checks.

    Common misconceptions

    • Coverage percent alone proves release readiness.

    • More compression always means better outcome.

    • Silicon mismatch can be debugged without pattern/tester traceability.

    • Shift timing and test power can be signed independently.

    Visual reinforcement

    ATPG flow

    Diagram
    fault models -> constraints -> generation -> coverage closure -> signoff

    Layer responsibilities

    Diagram
    DFT OWNERSHIP LAYERS - Coverage Closure
    
    layer              owns                         failure mode
    ----------------   --------------------------   -------------------------
    rtl/architecture   scanability hooks            uncontrollable logic
    atpg/constraints   legal pattern intent         aborts, low coverage
    physical/clocking  chain route + test clocks    shift hold/timing escapes
    tester/program     pattern apply integrity      false binning / bad fails
    quality signoff    release criteria             escapes or schedule slip

    DFT deep dive

    ATPG quality comes from fault model choice plus legal constraints, not raw pattern volume alone.

    Concept diagram

    Diagram
    ATPG FLOW
    
    fault model -> constraints -> generation -> simulation -> coverage closure -> signoff

    Metric graph

    Diagram
    COVERAGE GAP
    
    target coverage
      ^
      |      o before closure
      |          o after fixes
      +---------------------> iteration

    Reports and artifacts

    • fault model coverage

    • untestable class report

    • constraint legality errors

    • pattern signoff memo

    Mini case study

    Transition coverage stalled due to clock constraints mismatch; updated at-speed capture definitions recovered target.

    Debug branches

    • Classify untestable faults

    • Diff ATPG constraints each run

    • Pair coverage with pattern budget

    Senior review question

    Ask: what evidence proves this DFT decision is safe for production?

    Key takeaways

    • State metric, lot/corner context, and pattern tag with every claim.

    • Treat timing, power, and quality as one signoff problem.

    Common pitfalls

    • Chasing coverage without legality checks.

    • Ignoring test-power side effects of pattern changes.

    • Debugging silicon without reproducible tags.

    Theory reinforcement

    ATPG is a model-driven search constrained by legal test behavior.

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    See also

    • Coverage Closure: Mechanism
    • Coverage Closure: Inputs & Outputs
    • Coverage Closure: Reports & Metrics