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Course contents

  • How to Use This Course
  • DFT Metrics Reference
  • DFT Glossary
  • Reading Path
  • Scan Fundamentals61
  • Compression & Diagnosis61
  • ATPG & Pattern Generation61
  • MBIST & LBIST61
  • Boundary Scan & JTAG61
  • Test Timing & Power61
    • Test-Mode SDC
    • Shift vs Capture Timing
    • Test Power & IR
    • Test Signoff Reports
      • Test Signoff Reports: Mechanism
      • Test Signoff Reports: Inputs & Outputs
      • Test Signoff Reports: Reports & Metrics
      • Test Signoff Reports: Debug Playbook
      • Test Signoff Reports: Worked Example
      • Test Signoff Reports: Pitfalls & Red Flags
      • Test Signoff Reports: Interview Drills
      • Test Signoff Reports: Review Checklist
      • Test Signoff Reports: Theory Deep Dive
      • Test Signoff Reports: Design Space
      • Test Signoff Reports: Expanded Case Study
      • Test Signoff Reports: Step-by-Step Walkthrough
      • Test Signoff Reports: Comparison Matrix
      • Test Signoff Reports: Software / Programmer View
      • Test Signoff Reports: Silicon PPA Impact
    • Test Timing & Power: Tricky Q&A
  • DFT Physical Integration61
  • DFT Interview Prep61
  • DFT / ATPG Cheatsheet
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‹Test Signoff Reports
  1. Topics
  2. Design for Test
  3. Test Timing & Power
  4. Test Signoff Reports
  5. Test Signoff Reports: Debug Playbook

DFT / ATPG · All levels

Test Signoff Reports: Debug Playbook

Debug Playbook for Test Signoff Reports.

On this page

    Debug playbook

    Debug Playbook for Test Signoff Reports focuses on test readiness score, unresolved waivers, production release risk. The goal is to convert metric movement into mechanism, owner, and release decision.

    Debug aims to find the first incorrect assumption, not the loudest downstream symptom. Start with reproducibility and ownership.

    Root-cause tree

    Diagram
    ROOT-CAUSE TREE - Test Signoff Reports
    
    test readiness score, unresolved waivers, production release risk regresses
            |
      setup changed?
        /        \
      yes         no
      |            |
    constraint    silicon or
    or ATPG       physical/test path
     /    \          |
    SDC   model    chain/clock/power/diagnosis
    diff  diff     isolate first failing signature
    1. Freeze run tags for patterns, constraints, and tester setup.

    2. Isolate first failing metric bucket and scenario.

    3. Classify failure source: model, constraints, physical, or silicon.

    4. Prove mechanism with one reduced replay or targeted run.

    5. Apply smallest owner-controlled fix.

    6. Re-run timing, power, and quality regression matrix.

    Review memo template

    Diagram
    STAFF DFT REVIEW MEMO - Test Timing & Power / Test Signoff Reports
    
    1. Symptom
       - Watched metric: test readiness score, unresolved waivers, production release risk
       - Failing scenario: <mode/lot/corner/program>
       - Pattern class: <scan/transition/compressed/BIST/JTAG>
       - Tags: <constraints, patterns, tester program, netlist>
    
    2. Mechanism hypothesis
       - Primary mechanism: Test signoff consolidates coverage, timing, power, and diagnosis evidence into a release decision with explicit ownership and waivers.
       - Competing hypothesis: <constraint issue, model issue, physical issue, silicon issue>
       - Missing evidence: <report, replay, diagnosis trace>
    
    3. Proposed action
       - Minimal reversible change: <constraint fix, architecture tweak, pattern update>
       - Expected metric movement: <delta>
       - Regression risk: timing, power, quality, schedule
    
    4. Signoff
       - Re-run artifact: test signoff dashboard, waiver tracker, release review memo
       - Required owners: DFT lead, product engineering lead, program lead
       - Final decision: release, waive, rollback, or escalate

    DFT deep dive

    Test signoff fails when shift/capture timing and test power are treated independently.

    Concept diagram

    Diagram
    TEST SIGNOFF LOOP
    
    test SDC -> shift/capture timing -> power-aware ATPG -> IR validation -> release

    Metric graph

    Diagram
    TEST CURRENT
    
    functional current  baseline
    scan shift current  peak-risk zone

    Reports and artifacts

    • test-mode STA report

    • shift/capture split

    • test power IR map

    • waiver tracker

    Mini case study

    At-speed patterns passed timing but failed in production due to peak shift IR; staggered capture and power-aware fill resolved.

    Debug branches

    • Tag test and functional corners separately

    • Check hold in shift mode

    • Correlate fail bins with power hotspots

    Senior review question

    Ask: what evidence proves this DFT decision is safe for production?

    Key takeaways

    • State metric, lot/corner context, and pattern tag with every claim.

    • Treat timing, power, and quality as one signoff problem.

    Common pitfalls

    • Chasing coverage without legality checks.

    • Ignoring test-power side effects of pattern changes.

    • Debugging silicon without reproducible tags.

    Principal DFT review addendum

    Test signoff consolidates coverage, timing, power, and diagnosis evidence into a release decision with explicit ownership and waivers.

    Metric: test readiness score, unresolved waivers, production release risk

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    See also

    • Test Signoff Reports: Mechanism
    • Test Signoff Reports: Inputs & Outputs
    • Test Signoff Reports: Pitfalls & Red Flags