Timing closure depends on delays between flip-flops. This section covers STA foundations, setup and hold slack, skew, exceptions, clock gating, and RTL habits for closure.
Topic | Lessons | After it you can… | Study time |
|---|---|---|---|
5 | Explain what STA checks, read a flow, write a starter SDC. | 2 h | |
6 | Compute slack and choose the right fix for each violation. | 3 h | |
5 | Read a path report with clock latencies, uncertainty and derates. | 2–3 h | |
4 | Justify multicycle, false-path and case-analysis constraints. | 2 h | |
5 | Gate clocks safely with a latch-based ICG. | 2–3 h | |
7 | Apply depth budgets, fanout control and shallow structures. | 2 h | |
7 | Plan domains, switch clocks safely, write concrete SDC, and sequence DVFS. | 3–4 h |
Study time covers reading each lesson and running its examples. The section's hands-on project takes extra hours on top.
Not necessarily. You also need the flip-flops' clock-to-Q and setup times, skew, and uncertainty. A 2.0 ns period with 0.47 ns of clock-to-Q plus setup leaves only 1.53 ns for logic, so 1.8 ns fails. The setup/hold lessons show the full equation.
Use these four questions to decide whether you are ready to move on: explain, predict, implement and debug. If one is shaky, each answer names the lesson to revisit. New readers can skip this until they finish the section.
Setup compares data launched at one edge against the next capture edge, so the period is in the equation. Hold compares data launched at an edge against the capture at that same edge: the new data must not arrive before the capturing flop's hold window closes. Both sides refer to the same edge, so the period cancels, and slowing the clock never fixes a hold violation. Revisit Core equations and slack meaning.
Arrival = 0.15 + 1.6 = 1.75 ns. Required = 2.0 − 0.1 = 1.9 ns. Slack = 1.9 − 1.75 = +0.15 ns: the path meets setup with 150 ps to spare. Revisit Worked numeric examples.
set_multicycle_path -setup 2 on those paths, paired with set_multicycle_path -hold 1 on the same paths. Without the hold line the hold check moves with the setup check and becomes far too strict. Only do this when the RTL really guarantees the two-cycle spacing. Revisit Multicycle path setup and hold pairing.
Lowering the frequency does nothing for hold. Add delay on the data path (hold buffers or slower cells) or reduce the capture clock's late arrival, and recheck setup on that path afterwards. Revisit Fix strategy: setup vs hold.
Timing-aware simulations give every element a delay and check setup and hold windows, so a violation appears as an unknown (X) at the capture flop. The testbenches compare the simulated violations with the slack equations in both directions.
Logic-depth and cell numbers come from Yosys runs on the code shown, with the caveat that a generic area-oriented flow is not a timing-driven commercial flow. The trends are what matters.
Constraint (SDC) examples and timing reports are not machine-checked here; the numbers in the constructed reports are internally consistent and labelled as illustrations.