Timing & Clocking

What this section covers

RTL must meet clock period and I/O timing . This section connects pipeline intuition (Part 3) to STA graphs, constraints, and the RTL patterns that make closure predictable.

Topics in this section

1. STA intro — graphs, corners, and reporting

2. Setup, hold & slack — required vs arrival

3. Skew & uncertainty — margin budgeting

4. Multi-cycle & false paths — exceptions

5. Clock gating — ICG and enable timing

6. RTL for timing — retime-friendly structure

Timing arc

launch FF ──► net + cell delay ──► capture FF
     Tclk + Tcq              Tsetup
          └── slack = required − arrival ──┘

Key takeaways

• Start STA thinking after pipelining — each stage is one timing arc.

• Hold fixes differ from setup fixes (delay insertion vs logic restructuring).

• Clock gating touches Part 9 low-power and Part 6 CDC enable crossing.

Related topics

• Pipelining

• Retiming

• Setup/hold/slack

• Synchronizers (clock domain)

• STA ECO closure

• Timing/STA interview

Deep dive

This lesson deepens Timing & Clocking within timing. Senior reviewers expect you to connect mechanism to STA graphs, slack, constraints, and RTL structure for closure — not just define terms.

Start from the spec invariant: what must always be true each cycle? Write it as a Boolean relation, timing budget, or protocol rule before coding. That invariant becomes your reference model, assertion, or waveform check.

At tape-out quality, every block needs a sign-off story: SDC reviewed, exceptions justified, setup/hold clean. Treat this lesson as building one paragraph of that story for your project documentation.

Architecture and signal flow

TIMING & CLOCKING

  inputs ──► [timing] ──► mechanism ──► outputs
                │                │
           timing     verify in sim + lint

Worked example (Verilog/SystemVerilog)

Synthesizable pattern for this topic — simulate locally and compare against your reference.

// timing/timing: Timing & Clocking
module example;
  logic clk, rst_n;
  initial begin
    clk = 0; forever #5 clk = ~clk;
  end
endmodule

Step-by-step design procedure

1. Write the spec invariant (truth table, timing, or protocol rule).

2. Sketch block diagram — inputs, outputs, clock/reset domains.

3. Code the minimal correct version (no optimizations yet).

4. Run self-checking TB with corners: min, max, reset, idle.

5. Lint and review: width, latch, clock, CDC if applicable.

6. Iterate for timing/area only after functionally proven.

Timing and resource trade-offs

METRIC          TYPICAL LEVER
Logic levels      algebra / pipelining
Register count    retiming / sharing
Wire fanout       duplication / pipeline
Power             clock gating / operand isolation
Debug visibility  status flags / SVA / waveform probes

Debug checklist

• Compare DUT vs reference on every stimulus vector

• Capture first cycle of mismatch — not last

• Log seed and plusargs for random regressions

• Check reset release and clock alignment in TB

• If waveform is ambiguous, add temporary assertions

Interview angle

Setup failure fix order: RTL vs constraint vs physical?

MODEL ANSWER SKELETON
1. MECHANISM — one-sentence technical truth
2. MOTIVATION — why this structure vs alternatives
3. WHEN TO USE / SKIP — scope and assumptions
4. PITFALL — common junior mistake
5. EXAMPLE — Verilog or waveform scenario

Practice exercise

Extend the worked example for "Timing & Clocking": add one corner case, write a self-checking test, and document one intentional pitfall you avoided. Timebox: 30–45 minutes.

Common pitfalls

• Skipping reference model — passes wrong together with DUT.

• Optimizing before correct — ECO cost goes up 10×.

• Ignoring tool warnings — lint/CDC/STA warnings are technical debt.

• Undocumented clock/reset domain — integration surprises.

Extended design scenario

Scenario for Timing & Clocking : Setup failure on wide mux — pipeline select or duplicate late arriving bit.

Scenario resolution outline

1. Reproduce with minimal TB — one stimulus, one check.

2. Isolate failing cone (logic, FSM state, or bus beat).

3. Fix root cause — not symptom — in RTL or TB alignment.

4. Add regression test that fails without the fix.

5. Document invariant in comment or SVA for permanence.

Additional simulation pattern

// Annotate failing path in STA report
// launch: u_reg/CK -> capture: u_out/D

Synthesis and sign-off notes

• Elaborate clean — no OOM from unconstrained generate

• Constraints cover all clocks and I/O delays

• Cross-check RTL parameters vs integration top

• Attach sim log + seed to code review

Lab exercise (45–60 min)

Implement or extend the worked example for "Timing & Clocking". Add two new test vectors that target different branches. Write a one-paragraph sign-off note covering function, corners, and what you would still verify in SoC context.

Further reading in this course

Next topics in Part: follow nav_order in sidebar.
Cross-part: timing ↔ sequential, CDC ↔ senior interview,
combinational ↔ foundations number systems.