Static timing analysis checks every path against the clock without input vectors. It needs a netlist, constraints and libraries, and RTL structure decides its result.
5 lessons, about 24 min
No. Functional simulation (without back-annotated delays) ignores delays entirely. Timing needs STA on the gate-level netlist with the constraints and the libraries.
The whole topic on one page, taken from each lesson's Remember box. Read it before an interview, or print it.
Where RTL Meets STA
A path runs from a flip-flop clock pin or an input port to a flip-flop data pin or an output port.
Yosys ltp -noff finds the longest combinational path. Inspect its start and end nets, because it is not limited to register-to-register paths.
Levels ignore wire delay and fanout, so a path with fewer levels can still be slower.
Rule of thumb: use depth as an early warning, and confirm it with real timing.
Canonical STA Flow
A run reads libraries, netlist, constraints and parasitics, checks the constraints, updates timing and reports slack.
Check the constraints first, then the worst path, then group failing paths by cause. Hundreds of failures are often one slow module.
Fix depth and fanout structurally in RTL. Use tool optimisation for the small remainder.
Rule of thumb: treat constraints as code, and read the unconstrained-endpoint report before trusting a clean summary.
Corners
Gate delay depends on process, supply voltage and temperature, and wires add RC corners.
Slow data often limits setup and fast data often limits hold, but the relative clock and data delays decide the worst view.
Check every mode (functional, test, sleep) at every relevant corner.
Rule of thumb: do not discard a hold failure in a slow view or a setup failure in a fast view.
SDC Starter Set
With a 2.0 ns clock, 0.8 ns input delay and 0.15 ns uncertainty, the input budget is 1.05 ns for logic plus setup.
The output budget is the clock period minus the output delay and uncertainty (1.25 ns here), for clock-to-Q plus logic.
Every false path needs a written justification.
Rule of thumb: a missing clock is silent, so check the unconstrained endpoints before you trust a clean summary.
Why RTL Architecture Dominates
Plain + specifies the sum and not a ripple structure. Synthesis can restructure carry logic, and an explicit prefix network expresses one candidate.
Five prefix stages are not five gate levels, so the mapped depth is higher.
Compare candidates on the same library, constraints and physical flow before replacing portable arithmetic.
Rule of thumb: start from the path: how many levels, which operator dominates, and which lever fits.
Mini project: close timing on an 8-tap FIR filter
Interview: run a mock interview on this topic