A timing run reads four inputs, checks that the constraints cover the design, computes arrival and required times, and reports slack.
Read it top to bottom. Each box is one step of the run.
Libraries hold cell delay and constraint tables for one corner (process, voltage, temperature).
Netlist is the synthesized design, or the placed-and-routed design later in the flow. SDC gives clocks, input and output delays and exceptions.
Parasitics are wire resistance and capacitance after placement and routing. Before that, a wire-load estimate is used.
Check constraints asks: are all registers clocked? Any unconstrained endpoints? Any combinational loops? Update timing then computes arrival times at every pin and required times at every endpoint.
The report lists each endpoint with its slack. This constructed summary has three endpoints in one clock group, with a 2.00 ns clock and 0.12 ns setup.
Endpoint Clock Required Arrival Slack
u_alu/acc_reg[7]/D clk 1.88 1.93 -0.05 (VIOLATED)
u_alu/acc_reg[6]/D clk 1.88 1.89 -0.01 (VIOLATED)
u_ctl/state_reg[0]/D clk 1.88 1.68 +0.20 (MET)Required is when data must be there: the next edge minus setup and uncertainty. Here 2.00 - 0.12 = 1.88 ns, with no uncertainty.
Arrival is when the latest data actually gets there: clock-to-Q plus logic and wire.
Slack is required minus arrival. Negative means the endpoint fails by that much.
The summary of these three lines is WNS -0.05 ns (the worst) and TNS -0.06 ns (the sum of the two negative slacks).
Each report answers one question. The table lists the main ones.
Report | Question it answers |
|---|---|
Constraint check (unclocked registers, missing delays) | Is every path actually being timed? |
Worst paths by group | Which paths limit the clock? |
Setup ( | Do any endpoints fail either check? |
Timing summary (WNS, TNS) | How bad is it overall? WNS = worst negative slack, TNS = total negative slack. |
Clock network and skew reports | How well balanced is the clock? |
Work from constraints to structure. The list below gives the order.
First make sure the constraints are right; an over-tight or missing constraint wastes days.
Then look at the worst path: its startpoint, endpoint, the number of logic levels, the largest fanout on the path, and whether clock skew helps or hurts.
Group failing paths by cause. Hundreds of failing endpoints are often one slow module.
Fix structurally in RTL when the cause is depth or fanout; use tool optimisation for the small remainder.
No. Unclocked registers are not timed at all, so their paths are missing from the report. Fix the clock definition and rerun before trusting the result.