Clock architecture is a functional design contract before it becomes a CTS problem. RTL owners define sources, muxing, gating, switching sequences, domain relationships, reset release, and the constraints needed to analyze every legal mode.
One worked clock tree connects the lessons: a 100 MHz reference feeds a 400 MHz PLL, a glitch-free mux selects PLL or 25 MHz debug clock, an integrated gate drives the core, and a divide-by-four output clocks a peripheral. A forwarded strobe handles external data, while the core can enter a lower-voltage mode.
Read the tree from the top: every box is a source or a transformation that needs both functional control and a timing constraint.
Two unrelated sources (the 100 MHz reference and the 25 MHz debug clock) meet only at the glitch-free mux.
The ICG makes no new clock; the divide-by-four does, and needs a generated-clock constraint.
The strobe-captured data never shares a clock with the core: it crosses through an async FIFO.
7 lessons, about 25 min
Changing it while either clock is high can truncate a pulse or create an extra edge. Clock switching needs a dedicated glitch-free cell and protocol.
The whole topic on one page, taken from each lesson's Remember box. Read it before an interview, or print it.
Clock-Domain Plan
For every clock record source, frequency and modes, relationship, controls, consumers, reset and the owner of its constraints.
The relationship (synchronous, mesochronous, asynchronous or exclusive) drives both CDC analysis and clock-group constraints.
Each transformation, such as a divider, mux or gate, needs a functional control and a timing constraint.
Rule of thumb: the source generates the waveform; the owner defines its legal modes, controls, constraints and reset behaviour.
Glitch-Free Clock Mux
A glitch-free mux uses mutually exclusive, low-phase source enables and a stable select.
The controller drains the domain, requests the switch, waits for an acknowledgement that the new source is active, then resumes.
Use separate bounded timers. A timeout keeps work blocked and the domain isolated or in reset; it does not make a stopped-high clock safe.
Rule of thumb: never mux clocks as ordinary data, and never trust a clean zero-delay waveform as proof.
Generated and Virtual Clocks
A generated clock keeps the phase and frequency relationship to its master. A divider needs one.
Clocks propagate through ICGs and muxes, so a gated clock needs no definition of its own.
A virtual clock models the external device for input and output delays with no design pin.
Rule of thumb: every RTL clock divider needs a generated-clock constraint as well as a functional review.
PLL Lock and Reset Coordination
Synchronise lock, require it stable for a documented interval, then release reset synchronously in each destination domain.
Immediate containment on clock loss belongs to a clock-fault and reset controller, with outputs isolated and traffic masked.
After lock is lost, reacquisition is qualified again and resume follows a controlled sequence.
Rule of thumb: do not use raw pll_lock as reset deassertion.
Source-Synchronous Interfaces
Keep the high-speed capture in the IO or forwarded-clock domain, then cross into the core with a FIFO or handshake.
The budget needs earliest and latest data arrival and the setup and hold capture edges. One nominal waveform is not a constraint.
DDR needs separate rising and falling budgets, and deskew changes the edge relationship.
Rule of thumb: the forwarded strobe closes pin-to-IO timing only; the crossing into the core needs CDC analysis.
DVFS Transition Protocol
Raise voltage before frequency, and lower frequency before voltage.
Block new work, drain, switch the clock through approved hardware, wait for lock, select the matching timing mode, then resume.
Handle a quiesce timeout, no lock, a missing voltage acknowledgement, clock loss and an active CDC peer with a stated containment.
Rule of thumb: never increase frequency until the voltage acknowledgement has arrived.
Clock Constraint Examples
A generated clock at the PLL, then core and peripheral alternatives through the mux. Report both peripheral clocks with their periods and masters.
Supply both -max and -min input delays: max feeds setup and min feeds hold.
Audit unconstrained endpoints, check every legal mode independently, and review clock groups against CDC results.
Rule of thumb: show the SDC relationship for each clock, then close with coverage reports that prove the endpoints are constrained.
Mini project: close timing on an 8-tap FIR filter
Code lab: SDC clock groups
Code lab: Clock mux model
Interview: run a mock interview on this topic