Clock-Domain Plan

Part 5 · Timing & Clocking · Intermediate

For every clock	Record
Source	Port, PLL, divider, mux, or recovered clock
Frequency/modes	Nominal and legal dynamic values
Relationship	Synchronous, mesochronous, asynchronous, or exclusive
Controls	Gate enable, mux select, divider value, lock indication
Consumers	Registers, memories, interfaces, test logic
Reset	Assertion source and release synchronizer
Constraint owner	SDC definition and mode/view coverage

For the worked tree, this inventory distinguishes the related reference/PLL/peripheral clocks from the unrelated debug source and records that only one mux source is active in a functional scenario. That classification drives both CDC analysis and clock-group constraints.

Clock names in RTL, SDC, CDC waivers, UPF, and integration documents must refer to the same architecture. A missing generated clock can make valid paths unconstrained; a false asynchronous declaration can hide real timing.

Worked clock tree: a 100 MHz reference feeds a 400 MHz PLL; the PLL and a 25 MHz debug clock feed a glitch-free mux; the mux output passes an ICG into the 400 MHz core; a divide-by-four makes the 100 MHz peripheral clock; data captured on the forwarded strobe rx_strobe_i reaches the core through an async FIFO.

The worked tree as an inventory: each transformation needs functional control and a timing constraint.

Check yourself What is the difference between clock source and clock owner?

The source generates the waveform; the owner defines legal modes, controls, constraints, reset interaction, and signoff evidence for the domain.

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