Clock | Purpose | Typical constraint |
|---|---|---|
Primary | External/root waveform |
|
Generated | Derived by a divider (needed); optionally at a mux output to name each source |
|
Virtual | External launch/capture reference with no design pin |
|
Forwarded | Clock/strobe sent with data | Generated clock at output port |
Read the chart from the top: each label says which SDC command owns that point.
Primary clocks sit on ports where a waveform enters: create_clock.
Every box below a primary is generated from it, so STA keeps the edge relationship. The ICG adds no clock at all.
The virtual clock stands alone: it describes the external device for input and output delays.
A generated clock preserves phase and frequency relationship to its master. Recreating it as an unrelated primary clock loses that relationship and can cause incorrect cross-domain analysis.
Virtual clocks model the external device for input and output delays without pretending the clock physically enters the block.
In the worked tree, the divide-by-four peripheral clock needs a generated clock. Clocks propagate through ICGs and muxes automatically, so the gated core clock needs no definition of its own; a generated clock at the mux output is optional, used to name each source for exclusivity. The PLL output is defined per the PLL model: create_clock at the PLL output, or a generated clock with -multiply_by. The debug clock is a separate primary source, while the external forwarded-strobe interface uses its own boundary model.
Because STA would lose its edge relationship to the parent. A generated clock tells the tool which parent edges create child edges.