Inside the design STA sees real cells and wires. At the boundary it sees nothing, so the boundary constraints are a contract: how late data arrives at each input, and how early it must leave each output. This topic covers set_input_delay and set_output_delay, how to budget an interface, virtual clocks, and the audit that catches unconstrained ports.
Lesson | After it you can... |
|---|---|
Derive and apply boundary delays with the right min and max. | |
Split a period between outside and inside. | |
Use a clock that does not exist in the design as a reference. | |
Find missing or inconsistent port constraints. |
The arrival time of data at the input port relative to a clock edge, set by the external launching logic and board delay. It is not a delay added inside the block.