This section builds the model every later lesson uses: a design is a timing graph, every path is checked against a launch and a capture edge, and every number comes from a clock arrival, a cell or wire delay, and a margin. Nothing in the later sections (constraints, corners, variation, noise, closure) works without these four ideas.
Lesson | After it you can... |
|---|---|
Say what STA proves and what it cannot. | |
Compute latest arrival times on a small graph. | |
Classify any path and name what constrains it. | |
List the sources of pessimism and which are removable. | |
Find the time budget from the edge relationship. | |
Write and evaluate the setup inequality. | |
Write and evaluate the hold inequality. | |
Compute slack, WNS, TNS and the failing count. | |
Explain how the clock model moves slack. | |
Apply the three terms with the right signs. | |
Compute the shared-path credit. | |
Say how clocks through logic are timed. | |
Interpolate a delay table. | |
Estimate wire delay with the Elmore model. | |
Compute a load and set boundary models. | |
Describe the order of delay calculation. |
Suggested order: work the four topics top to bottom. Every lesson has a worked example; the Python blocks run, so change a number and see the slack move. For the RTL designer's view of the same ideas see STA Foundations and Setup, Hold and Slack.
The data arrival (launch clock arrival plus clock-to-Q plus path delay) and the required time (period plus capture clock arrival minus setup time and uncertainty). Their difference is the slack.