A gate-level simulation with a good testbench can still miss a timing failure, because the failing path may never be exercised by the vectors you ran. Static timing analysis removes that dependency: it examines all paths through the design and compares each against a timing requirement. Knowing exactly what that does and does not cover tells you which checks to rely on for signoff.
Question | STA | Simulation |
|---|---|---|
Does every register-to-register path meet setup and hold? | Yes, all structural paths | Only paths the vectors toggle, and only if delays are annotated |
Is the function correct? | No: STA does not know the intended behaviour | Yes, against a checker or reference |
Does a path ever actually toggle? | No: it assumes any path can | Yes, observable |
Is a clock domain crossing safe? | For related clocks it checks setup and hold but cannot judge protocol safety; between asynchronous groups it checks nothing, so crossings need separate CDC verification | Only for the scenarios run |
Is a glitch on a combinational node harmful? | Not by itself (noise analysis is a separate step) | Possibly, if the model is detailed enough |
How long does a full run take? | Minutes to hours for a whole chip | Hours to days for realistic activity |
STA turns the netlist into a graph of cells and wires with delays on the edges (the next lessons build this). Computing the latest and earliest arrival time at every node is a linear pass through the graph, so cost grows with design size, not with the number of input vectors. That is why it can sign off a billion-gate design that simulation could never exercise exhaustively.
Every path can be exercised. A path through a mux whose select can never take the needed value is still timed unless you tell the tool (a false path or a case-analysis constant).
The constraints are right. STA checks the design against the clocks, input delays and exceptions you give it. Wrong constraints give a confident wrong answer.
The delay models are right. Library data, parasitics and the corner definition decide the numbers. A perfect analysis with the wrong corner proves nothing.
Not necessarily wrong. STA assumes the path can toggle. If the register really is static in operation, the right fix is an explicit, justified constraint (a constant or exception with evidence), not ignoring the report. If it is not static, simulation simply never exercised the failing case.