Aggressor

A net whose switching changes the delay of, or injects noise into, a coupled neighbour (the victim).

AOCV

Advanced OCV: derates that depend on logic depth (and usually distance).

Arrival time

The time at which a signal reaches a node, measured from the launching clock edge at the source; the latest for setup, the earliest for hold.

Capture edge

The clock edge at the capture register against which a check is measured.

CDC (clock domain crossing)

A path between different clocks; one between asynchronous clocks needs synchronisation.

Clock gating check

A setup and hold check on the enable of a clock gate, so the gate output cannot glitch.

Clock latency

Delay from the clock source to a register's clock pin, source plus network.

Clock uncertainty

A margin subtracted from the setup budget (and added to the hold requirement) for jitter and unmodelled skew.

Clock-to-Q

The delay from a register's clock edge to new data at its output.

Common path pessimism removal (CRPR)

A credit that removes the double counting of the clock path shared by launch and capture when derates are applied.

Corner

A named set of process, voltage and temperature conditions with matching libraries; sometimes also an interconnect extraction corner.

Coupling capacitance

Capacitance between neighbouring wires; its effect on delay depends on whether the neighbour switches.

Delta delay

The change in a net's delay caused by switching neighbours.

Derate

A factor that scales delays to model variation: late above one, early below one.

Duty cycle

The fraction of the clock period that the clock is high.

Endpoint

The end of a timing path: a register data pin or an output port.

Exception

A constraint that changes how a path is timed: false path, multicycle path, minimum or maximum delay.

False path

A path declared not to be timed. It removes the check entirely.

Generated clock

A clock derived from another clock through logic, defined with its source and relationship (divide, multiply, invert).

Glitch

A pulse on a net that should be quiet, often from coupling; harmful if the receiver responds.

Hold check

The requirement that data stays stable for the hold time after the capture edge, so new data does not overwrite old.

Hold time

The time the data must remain stable after the capture clock edge.

Hold violation

A hold check with negative slack: data changed too soon.

ICG (integrated clock gating cell)

A cell that gates a clock with an enable while avoiding glitches.

Ideal clock

A clock modelled with zero network delay, before propagation is computed.

Input delay

A constraint stating when external data arrives at an input port relative to a clock edge.

Jitter

Cycle-to-cycle variation of a clock edge about its ideal position.

Latch

A level-sensitive storage element; transparent for one phase of the clock.

Launch edge

The clock edge at which the source register releases new data.

Library set

The group of timing libraries (cells, memories, IO, macros) loaded for one corner.

Mode

An operating configuration with its own clocks and constraints, such as functional, scan shift or test.

Multicycle path

A path allowed more than one cycle to meet setup; its hold side must be adjusted to match.

Near-critical

A path or endpoint with slack close to zero, within a chosen band.

NVP (violating paths)

The number of endpoints or paths with negative slack, depending on the report.

OCV

On-chip variation: the delay of identical cells differing across a die.

Output delay

A constraint stating the external logic delay plus the external setup requirement at an output port, relative to a clock edge.

Path group

A set of paths reported and prioritised together, usually by capture clock.

POCV

Parametric OCV: a per-cell sigma combined statistically along the path.

Propagated clock

A clock whose real network delays are used, as opposed to an ideal clock.

Pulse width check

A check that a clock phase is at least the minimum a cell requires.

Recovery time

The minimum time an asynchronous release must arrive before the next clock edge.

Removal time

The minimum time an asynchronous control signal must remain asserted after the clock edge; equivalently, its release must occur at least the removal time after that edge.

Required time

The latest time at which data may arrive at a node and still meet its check (for setup; for hold it is the earliest time data may arrive).

Scenario

A mode combined with a corner (and an interconnect corner): one complete analysis setup.

SDC

Standard design constraints format: the common text format for timing constraints.

Setup check

The requirement that data arrives at least the setup time before the capture edge.

Setup time

The time data must be stable before the capture clock edge.

Setup violation

A setup check with negative slack: data arrived too late.

Skew

The difference between the clock arrival times at two registers.

Slack

Required time minus arrival time for setup, with the sign convention that positive means the check passes.

Startpoint

The beginning of a timing path: a register clock pin or an input port.

Switching window

The earliest and latest times a net can switch; used to decide whether an aggressor can overlap a victim.

Temperature inversion

The effect that at low voltage some cells are slower when cold than when hot.

Time borrowing

A latch passing data that arrives after it opens, taking time from the following stage.

TNS

Total negative slack: the sum of negative slacks over endpoints.

Transition (slew)

The time a signal takes to change between logic levels; it affects the delay of the next cell.

Union

The worst slack per endpoint over views.

Useful skew

Deliberate clock skew used to move slack between neighbouring stages.

Victim

A net whose delay or voltage is affected by an aggressor.

Virtual clock

A clock defined with no source pin, used to describe external timing for I/O constraints.

WNS

Worst negative slack: the smallest slack among endpoints, per check type.