Setup and hold cover most paths, but a chip also has structures whose timing is different: latches that pass data for a phase of the clock, gates that must not glitch the clock, reset pins whose release is a timed event, and cells that constrain the clock waveform itself. Each has its own checks and its own ways of failing. This section teaches all four with worked numbers, so that none of them is a surprise in a signoff summary.
Lesson | After it you can... |
|---|---|
Name a latch's edges and checks. | |
Compute borrowed time and its effect downstream. | |
Follow borrowing through several latches. | |
Apply review rules for latch paths. | |
State gating setup and hold edges. | |
Compute enable slack and half-cycle budgets. | |
Diagnose gating violations. | |
Review gating end to end. | |
Compute both reset-release slacks. | |
Predict partial release. | |
Explain which reset edge is timed. | |
Review reset timing. | |
Compute pulse width slack. | |
Compute period slack at a macro. | |
Show how a tree narrows a phase. | |
Review these checks. |
Suggested order: top to bottom. Two waveforms in this section come from real simulations: the clock gating glitch and the reset release. Previous sections: Delay Graph and Path Analysis and Constraints and SDC.
Latches (borrowing and closing-edge setup), clock gates (enable setup and hold against the clock), asynchronous reset pins (recovery and removal) and cells with clock waveform limits (pulse width and minimum period).