Setup and hold compare data against a clock edge. Pulse width and minimum period check the clock itself at a pin: each phase must be long enough for the cell to respond, and the period long enough for its internal timing. This topic covers the two checks, how a clock tree distorts the duty cycle, and the signoff rules.
Lesson | After it you can... |
|---|---|
Compute pulse width slack for both phases. | |
Compute period slack and relate it to dividers. | |
Show how a tree narrows one phase. | |
Review and fix these checks. |
Related background: Clock Architecture and Skew and Uncertainty.
Setup and hold relate data to a clock edge. Pulse width looks at the clock alone, at one pin, and needs no data path at all.