Pulse width and period checks are sometimes left out of the main summary because they do not involve data paths. They matter for exactly the cells that are most expensive to fix late: memories and macros. A short list prevents their omission.
Item | Evidence |
|---|---|
Checks are enabled and reported | A pulse width and period section in the signoff summary |
All macros and latches are covered | List of clock pins with limits, and a count of checks |
Both phases, every corner | Per-view table of worst high and low slack |
Propagated clocks used | Checks are against leaf arrival times, not the ideal clock |
Distortion reviewed | Duty cycle at the leaves, per corner |
Period limits match the clock definitions | Divided and multiplexed clocks reviewed |
views = {
"ss_0p72v_125c": {"high": 0.05, "low": -0.04},
"ff_0p88v_m40c": {"high": 0.11, "low": 0.09},
"tt_0p8v_25c": {"high": 0.08, "low": 0.03},
}
fails = {v: [ph for ph, s in d.items() if s < 0] for v, d in views.items() if min(d.values()) < 0}
assert fails == {"ss_0p72v_125c": ["low"]}
worst_high = min(d["high"] for d in views.values())
assert worst_high == 0.05
print("PASS: failing views and phases", fails, "; worst high slack", worst_high)Only the slow corner fails, and only the low phase: one phase in one corner points to duty cycle distortion, because rise and fall delays differ by corner, rather than to a frequency problem: with symmetric limits a frequency problem fails both phases together, while with asymmetric per-phase limits the tighter phase fails first, so state both limits before diagnosing. The fix is on the clock tree, and the next review reads the leaf duty cycle.
Symptom | Fix |
|---|---|
One phase narrow in the slow corner | Reduce rise/fall mismatch in the tree |
Both phases fail together (with symmetric limits; with asymmetric per-phase limits the tighter phase fails first, so state both limits before diagnosing) | Clock too fast for the cell: use a slower or divided clock |
Period violation at a macro | Divider or separate macro clock |
Pulse width at a gating cell | Review enable and gate cell, and the clock before the gate |
The check is at the cell's clock pin, which sees the waveform after the whole tree. The source waveform is only the starting point.