Why it matters

A flop or macro needs its clock to stay high long enough to latch internal nodes, and low long enough to precharge or reset them. A phase that is too narrow can fail even when every setup and hold check passes. The cell library gives the limits, and STA compares them with the clock waveform at the pin.

The check

high slack = (width of the high phase at the pin) - (minimum pulse width, high)
low slack  = (width of the low phase at the pin)  - (minimum pulse width, low)
width of a phase = (opposite edge arrival) - (this edge arrival), at the pin, for that corner

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# Ideal clock, period 1.00 ns (1 GHz), 50% duty. Memory pin limits (illustrative): high 0.42, low 0.42 ns.
period, duty = 1.00, 0.50
high, low = period * duty, period * (1 - duty)
min_high, min_low = 0.42, 0.42
slack_high = high - min_high
slack_low = low - min_low
assert abs(high + low - period) < 1e-9
assert abs(slack_high - 0.08) < 1e-9 and abs(slack_low - 0.08) < 1e-9
# the same pin at 1.25 GHz (period 0.80): 0.40 per phase
period2 = 0.80
slack2 = period2 * 0.5 - 0.42
assert abs(slack2 - (-0.02)) < 1e-9
print("PASS: slack at 1 GHz", round(slack_high, 2), "; at 1.25 GHz", round(slack2, 2))

At 1 GHz with a 50% duty cycle each phase is 0.50 ns, so a 0.42 ns limit leaves 0.08 ns of slack on both. Push the clock to 1.25 GHz and each phase is 0.40 ns: the limit is missed by 0.02 ns on both phases at once. Frequency alone, with a perfect duty cycle, can therefore violate the check; it does not need distortion.

Where limits come from

What the review looks for

• Pulse width checks are reported and clean for both phases, in every corner.

• The worst case is read at the pin, after the clock tree, not at the clock source.

• A violation is reported as a high or low phase specifically, since the fixes differ.

Related topics

• Next: Minimum Period