An asynchronous reset takes effect immediately, with no clock edge involved, so asserting it needs no setup check. Releasing it is different: if the reset lets go close to a clock edge, the flop may or may not take that edge, and may go metastable. The release is therefore timed with two checks that mirror setup and hold, called recovery and removal. This topic covers the checks, the reset network, why assertion and release are treated differently, and signoff.
Lesson | After it you can... |
|---|---|
Compute both slacks for a reset release. | |
Predict a partial release from tree skew. | |
Say which edge of a reset is timed and why. | |
Review and fix reset timing. |
The circuit-level side (reset synchronisers) is in Reset Synchroniser Structure; the constraints side is in CDC Constraints and STA.
Recovery resembles setup: the release must arrive early enough before the clock edge. Removal resembles hold: the release must not arrive too soon after the edge that the flop was supposed to still see in reset.