A clock gate passes or blocks a clock according to an enable. If the enable changes while the clock is in the wrong phase, the gated clock gets a runt pulse. Timing analysis checks that the enable is stable at the right moments, using setup and hold checks on the gate itself. This topic covers the check model, enable timing, typical failures and signoff.
Lesson | After it you can... |
|---|---|
State the setup and hold edges for AND and OR gates. | |
Compute enable slack against the clock. | |
Diagnose and fix typical failures. | |
Review gating checks end to end. |
The RTL-side view is in Clock Gating; the generated clock and path model is in Generated and Gated Clock Paths.
The gate combines the clock with the enable. If the enable changes while the clock is active it can cut a pulse short or create a spurious one; the checks guarantee the enable only changes in the safe phase.