Clock gating saves power and is common, so a chip can have thousands of gates. A gating bug is a functional failure that appears only at certain voltages or temperatures. A small, strict signoff list prevents it.
Item | Evidence |
|---|---|
Number of gates equals number of checked gates | Counts from the netlist and the check report |
Setup and hold clean in every corner | Per-view reports |
Enable launch edges documented | Table of gates and enable sources |
No gate relies on disabled checks | The exception list is clean |
Clock tree balances gated and ungated branches | Skew report across the gate |
ICG cells used or the custom structure justified | Review note |
gates, checked = 4820, 4818
missing = gates - checked
assert missing == 2
views_clean = {"ss_0p72v_125c": True, "ff_0p88v_m40c": True, "tt_0p8v_25c": False}
open_views = [v for v, ok in views_clean.items() if not ok]
assert open_views == ["tt_0p8v_25c"]
ready = missing == 0 and not open_views
assert ready is False
print("PASS: not ready: missing checks", missing, "open views", open_views)The review fails on two counts: two gates lack a check, and one view is not clean. A gating signoff states both numbers explicitly so nothing is hidden in a summary percentage. The two unchecked gates are the more dangerous: a gate with no check is one whose glitch risk nobody has assessed.
The gate count and checked count match, with each gap individually explained.
Results cover all corners, since gating margins vary strongly with voltage and temperature.
Gating signoff is repeated after every ECO that touches an enable or the clock tree.
An ECO can change enable delays or clock tree balance, which moves both gating checks. A previously clean gate may now violate setup or hold.