Enable logic is often wide and slow (a decode of state and requests), and its timing is tight because it must settle in the clock's low phase, often half a period. Understanding this half-cycle budget explains why gating enables are among the first paths to fail.
# Enable launched by a rising-edge flop; AND-gate setup is against the NEXT rising edge, i.e. a full period.
# But if the enable flop is a negative-edge flop, the budget is half a period.
T = 4.0
cq, logic, setup = 0.40, 1.20, 0.10
def slack(launch_edge, capture_edge):
return (capture_edge - setup) - (launch_edge + cq + logic)
full = slack(0.0, T) # rising-edge launch, next rising edge
half = slack(T / 2, T) # falling-edge launch, next rising edge
assert abs(full - 2.30) < 1e-9 and abs(half - 0.30) < 1e-9
assert half < full
print("PASS: enable slack full-cycle", round(full, 2), "half-cycle", round(half, 2))The same enable logic has 2.30 ns of slack with a rising-edge launch flop and only 0.30 ns when launched by a falling-edge flop, because the budget halves. The choice of launch edge for the enable is therefore a design decision with timing consequences, often made to satisfy the hold side of the check.
Enable source | Typical timing |
|---|---|
Rising-edge flop | Full-cycle setup, but hold needs a minimum path longer than half a period, so it is rarely used with an AND gate |
Falling-edge flop | Half-cycle setup; hold naturally safe |
Latch (ICG cell) | Both setup and hold are checked against the rising clock edge at the cell; the internal latch holds the enable through the high phase, so a rising-edge launch gets a full cycle |
Combinational from inputs | Defined by input delays; usually the tightest |
Enable paths are checked with the half-cycle relationship explicit where the launch is the opposite edge.
Enable logic depth is bounded by the gating budget, with margin.
ICG cells are used where possible: their built-in latch converts a half-cycle problem into a simpler check.
Its launch is half a period before the capturing rising edge, so the available time is T/2 = 2.0 ns less setup, and the 0.40 + 1.20 = 1.60 ns path leaves 0.30 ns.