STA Mastery · All levels

STA Mastery Cheatsheet

Dense reference for timing closure, signoff, and interview answers.

Debug order

diagram

CORNER/MODE/VIEW -> PATH GROUP -> METRIC -> ARTIFACT -> ECO -> REGRESSION

SDC: clocks, generated_clock, IO delay, false_path, multicycle
Graph: WNS, TNS, cell vs net, launch/capture clock
MMMC: corner x mode x lib x SPEF -> worst WNS
Variation: OCV / AOCV / POCV derate policy
SI: delta delay + noise -> spacing/shield/reroute
ECO: setup fix -> hold check -> SI -> full matrix

Questions before proposing ECO

Which corner/mode/view fails?
Which path group and endpoint?
Constraint bug, view mismatch, or real path?
Cell-heavy or net-heavy critical path?
What hold and SI regression will you run?

Practice this lesson