Each route is an ordered list. Read it top to bottom; each item assumes the ones above it.

Design engineer (about 14 hours)

1. What STA Checks and Setup and Hold Checks.

2. Clocks in Timing and Delay Models.

3. Clock Definition and Uncertainty, Generated Clocks and Exceptions.

4. Graph Traversal and Slack and Report Timing Deep Read.

5. Clock Gating Checks and Recovery, Removal and Async.

Implementation and signoff engineer (about 30 hours, without interview prep)

1. Foundations and constraints as above, in full.

2. Delay Graph and Path Analysis and Beyond Setup and Hold.

3. Corner and Mode Matrix Design, Library Sets and Operating Conditions and Signoff vs Implementation Views.

4. OCV, AOCV and POCV Mechanisms and Derate Policy and Approval.

5. Delta Delay Mechanism and SI Signoff Reports.

6. Setup and Hold Closure Order, then the Debug Playbook, then the Capstone.

Interview (about 10 hours)

1. STA Whiteboard Framework: the four-step answer, the drawing and the rubric.

2. Framework Drills: all three sets, timed.

3. Skim Setup Check Derivation, Common Path Pessimism Removal and Temperature Inversion.

4. The three scenarios: MMMC Storm, ECO Under Pressure and Constraint Ghost.

5. Q&A Bank, then the expanded bank and its rapid-fire round.

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