Delay Models · sta

Part 1 · Timing Paths and Checks · All levels

4topics
4lessons

A timing graph is only as good as the delays on its arcs. This topic explains how those delays are produced: cell delay from library tables that depend on input slew and output load, wire delay from parasitics, the loads and drivers at the boundaries, and the order in which a tool calculates it all.

Lesson	After it you can...
Cell Delay Tables and Slew	Interpolate a delay table and say why slew matters.
Net Delay and Parasitics	Estimate a wire's delay with the Elmore model.
Loads and Driving Cells	Compute a driver's load and set boundary conditions.
How Delay Calculation Flows	Explain the order of calculation and why results are reproducible.

Suggested order: page order. Constraints that set boundary loads and drivers are covered in the constraints section.

Check yourself Why can the same cell have different delays in two places in a design?

Because its delay depends on the input slew (set by the driver upstream) and on the output load (fanout pin capacitances plus wire). The same cell type with a different slew or load has a different delay.

Up nextCell Delay Tables and Slew

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