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Course contents

  • How to Use This Course
  • Reading Path
  • STA Glossary
  • STA Metrics Reference
  • STA Mastery Cheatsheet
  • Timing Paths and Checks16
    • What STA Checks
    • Setup and Hold Checks
      • Launch and Capture Edges
      • Setup Check Derivation
      • Hold Check Derivation
      • Slack and Criticality
    • Clocks in Timing Analysis
    • Delay Models
  • Constraints & SDC Fundamentals20
  • Delay Graph & Path Analysis16
  • Beyond Setup and Hold16
  • Multi-Corner Multi-Mode Signoff16
  • OCV, AOCV, POCV and Variation16
  • Crosstalk and Noise16
  • ECO and Closure16
  • STA Debug Playbook16
  • STA Interview Prep26
  • Capstone Timing Signoff Lab4
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‹Timing Paths and Checks
  1. Topics
  2. Static Timing Analysis
  3. Timing Paths and Checks
  4. Setup and Hold Checks

Part 1 · Timing Paths and Checks · All levels

Setup and Hold Checks

Which edge launches, which edge captures, and the two inequalities every register-to-register path must satisfy.

  • 4topics
  • 4lessons

Setup and hold are the two checks at the heart of STA. Setup asks whether data arrives early enough before the capture edge; hold asks whether it stays long enough after the edge it must not disturb. This topic derives both inequalities from the launch and capture edges, works numeric examples, and defines slack, WNS and TNS.

Lesson

After it you can...

Launch and Capture Edges

Name the launch and capture edge for any pair of flops.

Setup Check Derivation

Write and evaluate the setup inequality with latencies and uncertainty.

Hold Check Derivation

Write and evaluate the hold inequality and say why the period does not appear for same-edge paths on one clock.

Slack and Criticality

Compute slack, WNS and TNS from a list of endpoints.

Suggested order: the four lessons in page order. Setup, Hold and Slack gives the RTL designer's version of the same idea.

Check yourself Which check depends on the clock period, setup or hold?

Setup. Data has one full period (adjusted for the edge relationship) to arrive. Hold compares data launched at an edge with the capture of the previous data at the same edge, so for same-edge paths on one clock the period does not appear.

Interview

Write both inequalities on the board before you are asked. Setup involves the period and the max delays; for same-edge paths on one clock, hold involves neither the period nor the max delays. That asymmetry is the single most common follow-up.

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See also

  • What STA Checks
  • Clocks in Timing Analysis
  • Delay Models