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Course contents

  • How to Use This Course
  • Reading Path
  • STA Glossary
  • STA Metrics Reference
  • STA Mastery Cheatsheet
  • Timing Paths and Checks16
    • What STA Checks
    • Setup and Hold Checks
      • Launch and Capture Edges
      • Setup Check Derivation
      • Hold Check Derivation
      • Slack and Criticality
    • Clocks in Timing Analysis
    • Delay Models
  • Constraints & SDC Fundamentals20
  • Delay Graph & Path Analysis16
  • Beyond Setup and Hold16
  • Multi-Corner Multi-Mode Signoff16
  • OCV, AOCV, POCV and Variation16
  • Crosstalk and Noise16
  • ECO and Closure16
  • STA Debug Playbook16
  • STA Interview Prep26
  • Capstone Timing Signoff Lab4
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‹Setup and Hold Checks
  1. Topics
  2. Static Timing Analysis
  3. Timing Paths and Checks
  4. Setup and Hold Checks
  5. Setup Check Derivation

Part 1 · Timing Paths and Checks · All levels

Setup Check Derivation

Setup requires the latest data arrival to precede the capture edge by at least the setup time, after clock latencies and uncertainty.

On this page

    Why it matters

    The setup inequality is the one equation behind most timing reports. Write it once with every term and you can explain any setup violation: which term is too large, which is too small, and what a fix actually changes.

    The inequality

    Let the launch flop's clock arrive at time L (its clock latency), the capture flop's at C, the period be T, and the path have clock-to-Q delay D_cq, combinational delay D_path (the maximum), setup time S and clock uncertainty U. The data arrives at the capture flop at L + D_cq + D_path. The capture edge arrives at T + C, and the data must be stable S before it, with the uncertainty taken as margin. Setup holds when:

    Diagram
    arrival  = L + D_cq + D_path
    required = T + C - S - U
    slack    = required - arrival
    setup met  <=>  slack >= 0

    A worked example (illustrative numbers, ns)

    Term

    Value

    Role

    T

    2.00

    Clock period

    L

    0.30

    Launch clock latency

    C

    0.35

    Capture clock latency

    D_cq

    0.40

    Clock-to-Q of the launch flop

    D_path

    1.00

    Maximum combinational delay

    S

    0.10

    Setup time of the capture flop

    U

    0.10

    Clock uncertainty (setup)

    example.py
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    T, L, C, Dcq, Dpath, S, U = 2.00, 0.30, 0.35, 0.40, 1.00, 0.10, 0.10
    arrival = L + Dcq + Dpath          # 1.70
    required = T + C - S - U           # 2.15
    slack = required - arrival         # 0.45
    assert abs(arrival - 1.70) < 1e-9 and abs(required - 2.15) < 1e-9 and abs(slack - 0.45) < 1e-9
    # What does a 0.5 ns slower path do? The slack goes negative:
    assert required - (L + Dcq + Dpath + 0.5) < 0
    print("PASS: setup slack =", round(slack, 2), "ns")

    Slack is +0.45 ns, so setup is met with margin. A path 0.5 ns slower fails by 0.05 ns. Notice that later capture latency C helps setup (it gives the data more time) and later launch latency L hurts it. That is the whole idea behind useful skew.

    What a fix changes

    Change

    Effect on setup slack

    Shorter combinational path (resizing, restructuring)

    Improves by the delay removed

    Faster launch flop (smaller clock-to-Q)

    Improves by the reduction

    Later capture clock (useful skew)

    Improves, but hurts the capture flop's own outgoing paths

    Longer period

    Improves by the extra period

    Smaller uncertainty

    Improves, but only if the margin was genuinely too large

    Common pitfall

    Forgetting that latencies are part of the equation. A path with identical logic can pass in one block and fail in another purely because of clock skew between the flops. Always read the launch and capture clock arrival in the report, not only the data path.

    Interview

    Be able to write the equation with seven terms (T, L, C, D_cq, D_path, S, U) in 20 seconds and to say which side of it each ECO touches. That is what "explain a setup fix" means.

    Check yourself In the worked example, how much later could the launch clock arrive (L) before setup fails?

    Slack is 0.45 ns and L enters the arrival with a plus sign, so L can increase by 0.45 ns (from 0.30 to 0.75 ns) before the slack reaches zero, assuming nothing else changes.

    Related topics

    • Launch and Capture Edges

    • Next: Hold Check Derivation

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    See also

    • Slack and Criticality