Data delays are only half of every timing equation. The other half is when each clock edge actually arrives at each flop. This topic covers how clocks are modelled before and after the clock tree exists, the vocabulary of latency, skew and uncertainty, how shared clock paths are credited back, and how clock paths through dividers and gates are analysed.
Lesson | After it you can... |
|---|---|
Say when each model is used and how it changes slack. | |
Define the three terms and apply them with the right signs. | |
Compute the credit for a shared clock segment. | |
Explain how clocks through logic are timed. |
Suggested order: page order. The clock tree itself, from the RTL side, is in Clock Architecture and Skew and Uncertainty.
Because both flops are clocked: the launch flop's clock arrival (L) adds to the data arrival and the capture flop's clock arrival (C) adds to the required time. Only their difference, the skew, changes the slack.