Real designs divide, gate and mux their clocks. If the tool does not know a divider's output is a clock, the flops it drives have no clock and their paths are unconstrained. If it knows, the delay through the divider or gate becomes part of those flops' clock latency. Understanding which parts of a path are clock network and which are data decides which constraint is missing when a report looks wrong.
Element | Treated as | Effect on analysis |
|---|---|---|
Buffer or inverter in the clock tree | Clock network | Adds to the latency of every flop below it |
Clock gate (AND/ICG) between source and flops | Clock network, plus a gating check on its enable | Its delay adds to latency; the enable is a data path timed against the gate |
Divider flop whose output feeds other clock pins | A generated clock needs defining | Without a definition the downstream flops have no clock |
Mux selecting between clocks | Clock network with two clock arrivals | Needs case analysis or clock groups so only valid combinations are timed |
# Latency of a flop clocked through a gate: sum of the cells on the clock path.
segments = {"root_buf": 0.20, "gate_cell": 0.15, "leaf_buf": 0.25} # ns, illustrative
latency_gated = sum(segments.values())
latency_ungated = segments["root_buf"] + segments["leaf_buf"]
assert abs(latency_gated - 0.60) < 1e-9
assert abs(latency_gated - latency_ungated - 0.15) < 1e-9
print("PASS: gating adds", round(latency_gated - latency_ungated, 2), "ns of latency to the gated flops")The gated flops see 0.60 ns of latency against 0.45 ns for ungated flops on the same tree, a 0.15 ns skew between the two groups. Paths crossing between the gated and ungated groups therefore see that skew unless clock tree synthesis balances it. That is one reason clock gating is planned with the clock tree, not after it.
Every divider or toggle flop that drives clock pins has a generated clock defined; a count of unclocked flops confirms it.
Clock gates have a gating check on the enable path (covered in the advanced checks section).
Latency of gated and ungated branches is balanced, or the skew is deliberate and checked.
The divider output was never defined as a generated clock, so the flops below it have no clock. Add a generated clock definition for the divider output, with the correct source and division, and re-run.