These three words are used loosely in meetings and precisely in timing equations. Getting their definitions and signs right is what lets you predict, before you run anything, whether a clock change will help or hurt a path.
Latency is the time from the clock source to a flop's clock pin. Source latency is the delay outside the design (for example on-board or from a PLL); network latency is the delay through the on-chip clock network.
Skew between two flops is the difference of their clock arrival times. In this course, skew = C - L: the capture clock arrival minus the launch clock arrival. Positive skew means the capture clock is later.
Uncertainty is a margin subtracted from the available time for a check. It covers jitter, imprecise skew estimates before the clock tree is final, and other unknowns. It can differ for setup and hold.
Quantity | Setup slack | Hold slack |
|---|---|---|
Positive skew (capture later than launch) | Increases (more time) | Decreases (data must hold longer) |
Negative skew (capture earlier than launch) | Decreases | Increases |
Uncertainty | Subtracted from the available time | Added to the hold requirement |
# One path, skew swept: setup gains what hold loses.
T, Dcq, Dpath, Dmin, S, H, U = 2.00, 0.40, 1.00, 0.30, 0.10, 0.05, 0.05
L = 0.30
def setup(C): return (T + C - S - U) - (L + Dcq + Dpath)
def hold(C): return (L + Dcq + Dmin) - (C + H + U)
for skew in (-0.10, 0.0, 0.10, 0.20):
C = L + skew
print(f"skew {skew:+.2f}: setup {setup(C):+.2f} hold {hold(C):+.2f}")
# moving the capture clock later by 0.10 ns: setup +0.10, hold -0.10
assert abs((setup(L + 0.10) - setup(L)) - 0.10) < 1e-9
assert abs((hold(L + 0.10) - hold(L)) + 0.10) < 1e-9
print("PASS: skew trades setup slack against hold slack one for one")The sweep shows the exact trade: every 0.1 ns of positive skew adds 0.1 ns of setup slack and removes 0.1 ns of hold slack on this path. That one-for-one trade is why useful skew is a budget, not a free lunch.
Uncertainty values are defined per clock and per check and are documented as to what they cover (jitter, skew estimate, margin).
Large skew between flops on a critical path is intentional (useful skew) and checked in both setup and hold.
Source latency is per clock: on one clock it applies equally to launch and capture and cancels in register-to-register paths. It matters when the launch and capture clocks differ, or for input and output paths timed against a clock with a different source latency.
No: delaying the capture clock makes hold worse, since the capture clock arrival is on the required side of the hold equation. Fix hold by delaying the data or advancing the capture clock.