The previous topic assumed every flop sees the clock edge at the same instant. Real edges arrive at different times, wander between cycles, and vary across the chip.
Effect | Meaning | Models it |
|---|---|---|
Skew | Difference in clock arrival time between two flops (static, per path) | Propagated clock latencies after clock tree synthesis |
Jitter | Cycle-to-cycle variation of the clock edge (dynamic) |
|
Variation (OCV) | Same-chip differences in delay from process, voltage, temperature gradients | Derating factors (OCV, AOCV, POCV) |
5 lessons, about 18 min
Skew = 0.80 − 0.62 = +0.18 ns. A later capture clock helps setup (more time) and hurts hold (the data must stay away longer).
The whole topic on one page, taken from each lesson's Remember box. Read it before an interview, or print it.
Skew and Jitter in Practical STA
Positive skew (capture later) gains setup time and loses hold margin. Skew belongs to the path, not to one flop.
Useful skew is a transfer: stage 1 gains 0.30 ns, stage 2 loses 0.30 ns, and the total stays 0.38 ns.
Skew is fixed once the tree is built. Jitter is statistical and enters through set_clock_uncertainty.
Rule of thumb: before you borrow slack with skew, check that the next stage has slack to give.
Uncertainty Modeling
Before the clock tree exists, uncertainty covers expected skew plus jitter plus margin. After it, skew is measured, so keep jitter and a small margin.
Uncertainty cuts slack on both setup and hold checks.
Keeping a large pre-CTS value after CTS counts skew twice.
Rule of thumb: update the uncertainty as the flow moves on, and never count the same skew twice.
Clock Tree and Skew Sources
Skew comes from unequal buffer depth, unequal loads, wire RC, gating cells, derived clocks, variation and crosstalk.
CTS balances skew, insertion delay and transition time, with power as a cost.
A design with fifteen derived clocks is a hard clock tree problem even when every module is small.
Rule of thumb: prefer a main-clock enable to a derived clock unless the architecture needs the divider.
Reading Timing Reports with Skew Context
Skew is capture latency minus launch latency. Only that difference matters, not the absolute latency.
Data arrival is launch latency + clock-to-Q + logic. Required time is period + capture latency - setup - uncertainty.
To find the problem, look at the biggest cell delay, the skew line and any large wire delay.
Rule of thumb: report the slack, the skew and whether it helped, the dominant cell, and your first fix.
OCV and AOCV Concepts
Setup derates launch and data late and the capture clock early. Hold reverses them.
CRPR removes pessimism only on the shared physical clock segment: 0.50 x (1.08 - 0.92) = 0.08 ns here.
AOCV derates by logic depth. Deep paths get less derate, one- or two-cell paths get more.
Rule of thumb: if a path fails only with derates, fix the structure, not the margin.
Mini project: close timing on an 8-tap FIR filter
Interview: run a mock interview on this topic